Via Alliance Semiconductor Co., Ltd.

Glenfly Tech Co., Ltd.

Glenfly Technology Co., Ltd.

Jackson State University

Huaisheng Zhang

Dacheng Liang

Renyu Bian

Boming Chen

Zhou Hong

Wei Zhang

Wei Wang

Deming Gu

Fengxia Wu

Xin Jin

Baohua Li

Tian Shen

Xiangxiang Chen

Heng Qi

Xiaowei Yao

Maoxin Sun

Ifedayo Victor Ogungbe

Zhulin Chang

Xinan Jiang

Juding Zheng

Chengxin Yin

Bing Yu

Disclosed are a thread construction method and device. The method includes: a workload is divided into a plurality of work groups; for any work group, a pattern type that matches a size of the any work group is selected, a target thread construction pattern is determined from a plurality of candidate thread construction patterns corresponding to the pattern type; a plurality of threads are constructed according to the target thread construction pattern; the threads are composed of a plurality of consecutive work items in the any work group; the work item index corresponding to at least one key work item in the work item sequence of each thread is cached and the work item index of each thread is obtained, which is configured to schedule the any work item corresponding to the thread to the processing unit.

Thread construction method and device

Disclosed are method and apparatus for loading task data, a computer device, a storage medium, and a computer program product. The method includes: analyzing various types of buffers involved in a task after the task is initiated, and determining whether each of the buffers satisfies a preset read-only buffer condition; determining a buffer satisfying the read-only buffer condition as a read-only buffer; mapping the read-only buffer into a matched read-only storage space based on space information of the read-only storage space and size information of the read-only buffer, and obtaining corresponding read-only mapping information; and loading task data in the read-only buffer into the matched read-only storage space based on the read-only mapping information. With the method, the loading efficiency of task data can be improved.

Method and apparatus for loading task data, and computer device

Embodiments and methods for a new class of potent non-peptidic covalent inhibitors of nsP2 cysteine protease that inhibit Venezuelan equine encephalitis virus's (VEEV) replication in neuroblasts are disclosed. More particularly, an acrylate and vinyl sulfone-based chemical series were investigated as promising starting scaffolds against VEEV and as inhibitors of the cysteine protease domain of VEEV's non-structural protein 2 (nsP2). The invention discloses compounds of Formula I and analogues for treatment of VEEV.

Covalent inhibitors of equine encephalitis virus

A graphics processing apparatus includes a tessellation circuit and a post-processing circuit. The tessellation circuit performs tessellation processing to subdivide a patch in an image frame into a plurality of triangles. The tessellation circuit further performs triangle striping processing to convert data of the plurality of triangles into data of a triangle strip. The post-processing circuit performs subsequent processing on the data of the triangle strip.

Graphics processing apparatus

An apparatus integrates arithmetic with logic operations. The apparatus includes a calculation device that calculates source data to generate and output first destination data. The apparatus further includes a normalization unit, coupled to the calculation device, that normalizes the first destination data to generate second destination data of a first type when receiving a signal indicating an output of first-type data, and normalizing the first destination data to generate the second destination data of a second type when receiving the signal indicating an output of second-type data.

Apparatuses for integrating arithmetic with logic operations

A method for improving image quality is provided. The method includes: receiving an image data and sensing information; dividing the image data into areas corresponding to different resolutions according to first parameter information, wherein the different resolutions correspond to different frequencies; rendering the areas in a single pass according to the sensing information and the different frequencies and outputting a rendered image data; and resolving the rendered image data into a final output image data with a first resolution according to second parameter information.

Method and virtual reality device for improving image quality

An apparatus for integrating arithmetic with logic operations contains at least a calculation device and a post-logic unit. The calculation device calculates source data to generate and output first destination data. The post-logic unit, coupled to the calculation device, performs a comparison operation for comparing the first destination data with 0 and outputs a comparison result.

A method for computing trigonometric functions, performed by an ALU (Arithmetic Logic Unit) in coordination with an SFU (Special Function Unit), is introduced to contain at least the following steps. The ALU computes a remainder r and a reduction value x* corresponding to an input parameter x. The SFU computes an intermediate function f(x*) corresponding to the reduction value x*. The ALU computes a multiplication of the reduction value x* by the intermediate function f(x*) as the computation result of a trigonometric function.

Methods and apparatuses for computing trigonometric functions with high precision

A method for calculating FP (Full Precision) and PP (Partial Precision) values, performed by an ID (Instruction Decode) unit, contains at least the following steps: decoding an instruction request from a compiler; executing a loop m times to generate m microinstructions for calculating first-type data, or n times to generate n microinstructions for calculating second-type data according to the instruction mode of the instruction request, thereby enabling ALGs (Arithmetic Logic Groups) to execute lanes of a thread. m is less than n and the precision of the first-type data is lower than the precision of the second-type data.

Methods and apparatuses for calculating FP (full precision) and PP (partial precision) values

A method for combining instructions, performed by a compiler, containing at least the following steps. First instructions are obtained, where each performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated mathematics operation. The first instructions are combined as one combined instruction according to data dependencies between the first instructions. The combined instruction is sent to a SP (Stream Processor).

Methods for combining instructions and apparatuses having multiple data pipes

A method for a programmable primitive setup in a 3D graphics pipeline is introduced to contain at least the following steps. Information about first and third primitives is obtained from a buffer. The information about all or a portion of the first primitives is packed and sent to an SS (Setup Shader) thread. Information about a second primitive to be clipped is packed and sent to a GBS (Guard-Band-clipping Shader) thread. The information about all or a portion of the third primitives is packed and sent to an AS (Attribute Shader) thread.

Growing community of inventors

Shanghai, China

Huaisheng Zhang