Adeia Semiconductor Bonding Technologies Inc.

Lasercomm Inc.

Invensas LLC

Huailiang Wei

Charles Gerard Woychik

Kishor V Desai

Chok J Chia

Qwai Hoong Low

Belgacem Haba

Cyprian Emeka Uzoh

Craig S Mitchell

Terrence Caskey

Michael Rosenblit

Michael Lysiansky

Craig Mitchell

Charles G Woychik

A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Low cost hybrid high density package

A microelectronic component with circuitry includes a substrate (possibly semiconductor) having an opening in a top surface. The circuitry includes a conductive via (possibly metal) in the opening. The opening has a first sidewall of a first material, and the conductive via has a second sidewall of a second material (possibly metal). At least at one side of the opening, the first and second sidewalls are spaced from each other at the top surface of the substrate but the first and second sidewalls meet below the top surface of the substrate at a meeting location. Between the meeting location and the top surface of the substrate, the first and second sidewalls are separated by a third material (possibly foam) which is a dielectric different from the first material. The third material lowers thermal stress in case of thermal expansion compared to a structure in which the third material were replaced with the second material.

Reduced stress TSV and interposer structures

A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.

A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.

Area array quad flat no-lead (QFN) package

An optical waveguide designed to generate positive dispersion when operated in a high order mode. The optical waveguide in one embodiment is designed to generate positive dispersion slope, in another embodiment to generate negative dispersion slope and in yet another embodiment nominally zero dispersion slope. In one embodiment the high order mode is the LP mode and in another embodiment the high order mode is the LP mode. In another embodiment the optical waveguide is a few mode fiber. In an exemplary embodiment the optical waveguide is used in combination with a mode transformer, such as a transverse mode transformer to achieve the desired high order mode.

Optical waveguide exhibiting strongly positive dispersion, and system utilizing same

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Allen, TX, United States of America

Huailiang Wei