Micron Technology Incorporated

Winbond Electronics Corporation

Winbond Electronics Corporation America

Hua Zheng

Jeffrey P Wright

Todd A Merritt

Timothy B Cowles

Michael Amiel Shore

Kamin Fei

Huy Thanh Vo

Joseph C Sher

Victor Wong

David D Siek

Paul M Fuller

Nicholas Van Heel

Adrian E Ong

Kurt D Beigel

Patrick J Mullarkey

Douglas John Cutter

Fan Ho

Kim M Pierce

Brett M Debenham

Teng Su

Dien S Luong

Hui Zhao

Yuan-Mou Su

Jae-Hyeong Kim

Data input and output circuits that support multi data rate and a number of timing schemes. In one design, a data output circuit includes an input multiplexer, data latches, an output multiplexer, and at least one output driver. The input multiplexer receives a set of data bits in a first order (e.g., odd and even) and provides the data bits in a second order (e.g., first and second). The data latches can latch the data bits with (1) a latch signal to satisfy memory access timing requirements and (2) a data write clock signal to satisfy output timing requirements. The output multiplexer multiplexes the latched data bits to provide time multiplexed data bits. The output driver(s) provide signal drive for the time multiplexed data bits. Clock signals with various timing characteristics can be used to allow the data output circuit to satisfy various timing requirements.

Data input and output circuits for multi-data rate operation

A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

System for testing integrated circuit devices

A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a &ldquo;asynchronous&rdquo; external clock signal and external clock enable signal to an internal &ldquo;synchronous&rdquo; clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

Synchronous dynamic random access memory device

A semiconductor device is provided comprising a die. A first set of plural components, other than interface components, are located on the die surface. A first conductor located on the die surface connects to each component of the first set. A second set of plural components, other than said interface components, are located on the die surface. A second conductor located on the die surface connects to each component of the second set. A bonding pad is located on the die surface such that the first set of components lie between the bonding pad and an edge of the die and the second set of components lie between the bonding pad and an opposing edge of the die. The bonding pad is for receiving or transmitting one or more signals via the first and second conductors. At least one lead frame finger extends to an edge of the die but does not overlie the die. A bonding wire connects the at least one finger to the bonding pad.

Semiconductor die pad placement and wire bond

High speed test system for a memory device

A redundant circuit that includes a combination of fuses and anti-fuses, and which may be used during various phases of the manufacturing process (e.g., during wafer test or final test) to replace a defective circuit. The redundant circuit includes (1) a replacement circuit (e.g., a redundant memory cell) that is configurable to replace a defective circuit, and (2) supporting circuitry for the replacement circuit. The support circuit is configurable to provide a control signal (e.g., to activate a word line) for the replacement circuit and further includes at least one fuse and at least one anti-fuse. The fuses or anti-fuses may be programmed to provide a programmed value (e.g., a programmed address) for the replacement circuit. The redundant circuit can be efficiently fabricated within a memory device, and may also be used for other circuits and applications.

Redundant circuit for memory device

A memory array architecture that supports block write operation and has many advantages over conventional memory array architectures. A memory array is partitioned into a number of (N) segments. Each segment includes at least one bit line. Each segment is associated with a local input/output (I/O) line that couples to zero or more bit lines within that segment. The bit lines are coupled to the local I/O line by controlling one or more column select lines associated with that segment. Each segment is also associated with a write driver that couples to the local I/O line. Each local I/O line has a length that is a portion of a length of the memory array. A block write operation is performed by concurrently driving one or more write drivers (up to N write drivers). Each write driver drives the bit lines coupled to the local I/O line associated with that write driver.

Memory array architecture supporting block write operation

Techniques and circuits for testing high-speed circuits using slow-speed input signals. Various designs for a &ldquo;stimulus&rdquo; generator are provided, which is capable of generating a high-speed stimulus based on, or in response to, one or more input signals. In one design, the generator includes two edge detectors coupled to a latch. Each edge detector receives a respective set of input signals and provides an intermediate signal. The latch receives the two intermediate signals from the two edge detectors and generates the output signal, which has a particular waveform pattern generated based on the active (e.g., leading) transitions in the two sets of input signals provided to the two edge detectors. In another design, the generator includes a ring oscillator that is enabled by one input signal, and further initiated by a pulse on another input signal provided to an input of a latch used to implement the oscillator.

Method and apparatus for testing high-speed circuits based on slow-speed signals

An integrated device includes a configuration circuit that is coupled to first and second bond pads and first and second conductive paths of the integrated device. The circuit receives a map signal that has a first value during a first operational mode of the integrated device and a second value during a second operational mode of the integrated device. In response to the first value, the circuit couples the first pad to the second conductive path. In response to the second value, the circuit couples the first pad to the first conductive path and the second pad to the second conductive path. The first operational mode may be a wafer test mode.

Circuit and a method for configuring pad connections in an integrated device

An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indicate that the device has passed the tests associated with the selected point in the process. Prior to performing further tests on the device, the element is read to verify that it passed previous tests in the test process. If the appropriate elements are not programmed, the device is rejected. A rejected device may be retested according to the previous test steps. Laser fuses, electrically programmable fuses or antifuses are used to store test results. The use of electrically writeable nonvolatile memory elements allows for programming of the elements after the device has been packaged.

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Fremont, CA, United States of America

Hua Zheng