Taiwan Semiconductor Manufacturing Comp. Ltd.

Hua-Yu Yang

Wei-Kun Yeh

Chi-Hsiang Lee

Chih-Heng Shen

An-Min Chiang

Chi-Hsin Lo

Wen-Cheng Chien

Sen-Fu Chen

Ching-Wen Cho

Hui-Chen Chu

Wen-Cheng Chang

An-Ming Chiang

An Ming Chiang

Chang-Jen Wu

An active pixel sensor cell, and the process for forming the active pixel sensor cell, featuring a pinned photodiode structure, and a readout region, located in a region of the pinned photodiode structure, has been developed. The process features the formation of a N&plus; readout region, performed simultaneously with the formation of the N&plus; source/drain region of the reset transistor, however with the N&plus; readout region placed in an area to be used for the pinned photodiode structure. The pinned photodiode structure is next formed via formation of a lightly doped N type well region, used as the lower segment of the pinned photodiode structure, followed by the formation of P&plus; region, used as the top segment of the pinned photodiode structure, with the N&plus; readout region, surrounded by the P&plus; region. The placement of the N&plus; readout region, in a region of the pinned photodiode structure, eliminates the need for a transfer transistor, for the active pixel sensor cell, and results in a higher signal to noise ratio, as well as lower dark current generation, than counterparts fabricated without the use of the process, and structure, of this invention.

Pinned photodiode structure in a 3T active pixel sensor

A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.

CMOS image sensor n-type pin-diode structure

A process of fabricating an image sensor cell, on a semiconductor substrate, with the image sensor cell exhibiting low dark current generation, and high signal to noise ratio, has been developed. The process features the use of a photoresist shape, used to protect a previously formed photodiode element, from an reactive ion etching procedure, used to define insulator spacers on the sides of a polysilicon gate structure, of a reset transistor structure This process sequence avoids damage to the surface of an N type component, of the photodiode element, resulting in the improved electrical characteristics, when compared to counterpart image sensor cells, in which the photodiode element was subjected to the insulator spacer definition procedure.

Process for fabricating a high quality CMOS image sensor

Device layouts are described which increase the photon current of a metal oxide semiconductor image sensor. The metal oxide semiconductor can be NMOS, PMOS, or CMOS. The key part of the photon current of the image sensors comes from the depletion region at the PN junction between the drain region and the substrate material. The layouts used significantly increase the area of this depletion region illuminated by a stream of photons. The layouts have a drain region which takes the shape of a number of parallel fingers perpendicular to the gate electrode, a number of parallel fingers parallel to the gate electrode, or a spiral. The drain regions of these layouts significantly increase the area of the drain depletion region illuminated by a stream of electrons.

Layout of an image sensor for increasing photon induced current

A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.

Method of manufacturing CMOS image sensor leakage free with double layer

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Hsin-Chu, Taiwan

Hua-Yu Yang