Numerical Technologies, Inc.

Asml Netherlands B.v.

Synopsys, Inc.

Hewlett-Packard Company

Other

Hua-Yu Liu

Luoqi Chen

Jun Ye

Yu Long Cao

Jiangwei Li

Christophe Pierrat

Hong M Chen

Michael E Kling

Wei Liu

Yong Liu

Kent Richardson

Zhi-Pan Li

Jiong Jiang

Melody W Ma

Yen-Wen Lu

Peng Liu

Youping Zhang

Geraint Owen

Youri Johannes Laurentius Maria Van Dommelen

Min-Chun Tsai

Weinong Lai

Wenjin Huang

Aiqin Jiang

Xiaoyang Li

En-Den D Liu

Michael Matthew M Crouse

Melody Ma

A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare.

Correction for flare effects in lithography system

A computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method including computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, at least some of the design variables being characteristics of the illumination source and the design layout, the computing of the multi-variable cost function accounting for lens heating effects; and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied.

Lens heating aware source mask optimization for advanced lithography

The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Pattern selection for full-chip source and mask optimization

A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields.

The present invention relates to a method of selecting a subset of patterns from a design, to a method of performing source and mask optimization, and to a computer program product for performing the method of selecting a subset of patterns from a design. According to certain aspects, the present invention enables coverage of the full design while lowering the computation cost by intelligently selecting a subset of patterns from a design in which the design or a modification of the design is configured to be imaged onto a substrate via a lithographic process. The method of selecting the subset of patterns from a design includes identifying a set of patterns from the design related to the predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes a similar predefined representation of the design as the set of patterns.

Method of pattern selection for source and mask optimization

The present invention relates generally to selecting optimum patterns based on diffraction signature analysis, and more particularly to, using the optimum patterns for mask-optimization for lithographic imaging. A respective diffraction map is generated for each of a plurality of target patterns from an initial larger set of target patterns from the design layout. Diffraction signatures are identified from the various diffraction maps. The plurality of target patterns is grouped into various diffraction-signature groups, the target patterns in a specific diffraction-signature group having similar diffraction signature. A subset of target patterns is selected to cover all possible diffraction-signature groups, such that the subset of target patterns represents at least a part of the design layout for the lithographic process. The grouping of the plurality of target patterns may be governed by predefined rules based on similarity of diffraction signature. The predefined rules comprise coverage relationships existing between the various diffraction-signature groups.

Selection of optimum patterns in a design layout based on diffraction signature analysis

The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

A system and a method for creating a focus-exposure model of a lithography process are disclosed. The system and the method utilize calibration data along multiple dimensions of parameter variations, in particular within an exposure-defocus process window space. The system and the method provide a unified set of model parameter values that result in better accuracy and robustness of simulations at nominal process conditions, as well as the ability to predict lithographic performance at any point continuously throughout a complete process window area without a need for recalibration at different settings. With a smaller number of measurements required than the prior-art multiple-model calibration, the focus-exposure model provides more predictive and more robust model parameter values that can be used at any location in the process window.

System and method for creating a focus-exposure model of a lithography process

Resolution enhancement techniques (RETs) aid in accurately transferring features on a layout to a wafer. Unfortunately, RETs may work well at one pitch but not another pitch. If image quality falls below an acceptable threshold at a certain pitch, then such a pitch is called a forbidden pitch. A cell library cell that can automatically avoid forbidden pitches is provided. In this method, evaluation points on edges of a feature in a cell can be analyzed based on a RET and a lithography model. Using this analysis, any forbidden pitch for the feature can be identified. Additionally, any forbidden pitch can be changed to an acceptable pitch, i.e. a pitch resulting in an acceptable image quality. The forbidden pitch information and the associated acceptable pitch information for the feature can be stored in a database to facilitate analyzing other features/cells.

Cell library that can automatically avoid forbidden pitches

Methods and apparatuses for preparing layouts and masks that use phase shifting to enable production of subwavelength features on an integrated circuit in close (optical) proximity to other structures are described. One embodiment selects from several strategies for resolving conflicts between phase shifters used to define features and (optically) proximate structures that are being defined other than by phase shifting. One embodiment adds additional phase shifters to define the conflicting structures. Another embodiment corrects the shape of the phase shifters in proximity to a conflicting structure. Resulting integrated circuits can include a greater number of subwavelength features even in areas that are in close proximity to structures that were not initially identified for production using a phase shifting mask.

Alternating phase shift mask design conflict resolution

One embodiment of the invention provides a system that uses simulation results to select evaluation points for a model-based optical proximity correction (OPC) operation. Upon receiving a layout, the system first selects critical segments in the layout, and then performs a dense simulation on the critical segments. This dense simulation identifies deviations (or low contrast) between a desired layout and a simulated layout at multiple evaluation points on each of the critical segments. Next, for each critical segment, the system selects an evaluation point from the multiple evaluation points on the critical segment based on results of the dense simulation. The system then performs a model-based OPC operation using the selected evaluation point for each critical segment.

Simulation-based selection of evaluation points for model-based optical proximity correction

A critical dimension, or width, of a feature, or a semiconductor device, can be measured to provide direct and meaningful information regarding the impact of line end shortening, or length, on the function of the device. Specifically, a location on the feature where the width will have an impact on device performance can be selected. Using a simulation, the width at that location can be computed. Given the difficulties of direct measurement of line end shortening and the relationship between the width measurement and the impact on device performance, better layout checking is facilitated than by standard measurements of line end shortening.

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Palo Alto, CA, United States of America

Hua-Yu Liu