Lattice Semiconductor Corporation

Other

Hua Xue

Ju Shen

Venkatesan Rajappan

Bertrand Leigh

Chris West

Mike Ray

Gilles Bosco

Mohan Tandyala

Mohana Tandyala

Nilanjan Chatterjee

Jianping Sun

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.

Mixed-width memory techniques for programmable logic devices

Various techniques are provided to generate designs for programmable logic devices (PLDs). In one example, a computer-implemented method includes selectively grouping a first plurality of logic components for a first design into a plurality of partitions. The method also includes selectively merging at least a subset of the partitions of the first design. The method also includes converting each partition into a corresponding first physical implementation for a PLD. The method also includes comparing the first plurality of logic components to a second plurality of logic components for a second design to identify changed and unchanged partitions. The method also includes converting each changed partition into a corresponding second physical implementation for the PLD. The method also includes combining the first physical implementations for the unchanged partitions, with the second physical implementations for the changed partitions.

Partition based design implementation for programmable logic devices

Systems and methods provide improved techniques directed to simultaneous switching output (SSO) noise, which for example may be applied during the programmable logic device design process. For example in accordance with an embodiment, a method of structuring simultaneous switching output (SSO) noise data for an electronic device includes collecting hardware data on SSO noise conditions; generating additional data on SSO noise conditions based on the hardware data; and structuring the hardware data and the additional data to form data tables for SSO noise calculations.

Simultaneous switching output noise estimation and reduction systems and methods

Systems and methods provide I/O signal placement algorithms, such as for a programmable logic device. For example, a performing input/output (I/O) signal placement to pins of an electronic device, in accordance with an embodiment, includes placing all pre-assigned I/O signals to their assigned pin locations; placing unassigned I/O signals to initial I/O pin locations; and performing a simulated annealing for the I/O signals placed at initial I/O pin locations, wherein the simulated annealing accounts for simultaneous switching output (SSO) noise requirements.

Input/output placement systems and methods to reduce simultaneous switching output noise

A security tag includes a tag body and an attaching pin for attaching the tag body to a protected article. The security tag further includes a locking mechanism for releasably preventing the attaching pin from being removed from the protected article. The locking mechanism is provided for mechanically or magnetically released the attaching pin for detaching the tag body from the article. In a preferred embodiment, the locking mechanism further includes a plurality of balls for tightly holding to the attaching pin for releasably preventing the attaching means from being removed from the article. The locking mechanism includes a mechanical unlocking probe finger for applying a mechanical force to release the balls from the attaching pin. The locking mechanism further includes an unlocking magnet for applying a magnet force to release the balls from the attaching pin.

Electronic article surveillance (EAS) tag compatible with mechanical and magnetic unlocking detachers

An algorithm is disclosed to partition input variables between a feeder logic block and a receiver logic block. For a given input variable partition, the algorithm assigns both a cost to the number of product terms cascaded from the feeder logic block to the receiver logic block as well as a cost that increases as the number of input variables assigned to the receiver logic block approaches its maximum input width. The costs for a variety of input variable partitions are tested to determine an optimal input variable partition.

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Saratoga, CA, United States of America

Hua Xue