Yangtze Memory Technologies Co., Ltd.

Hua Tan

Bo Yu

Xing Wang

Fanya Bi

Zhe Sun

Yaolong Gao

Dili Wang

Teng Zhou

Xuqing Jia

Hongtao Liu

XiangNan Zhao

Lei Jin

Chenhui Li

Yufei Feng

Xiaodong Xu

Da Li

Qian Sun

Wei Qi

Shuai Zhang

ChuangChuang Zhao

Wenping Chen

Guangyao Han

Yaoyao Tian

Huiping Sun

In certain aspects, a method for operating a non-volatile memory device is provided. The non-volatile memory device includes memory units. A write count of a first memory unit of the memory units is determined. In response to the write count of the first memory unit reaching one of preset values, a flipped bit count (FBC) of a second memory unit of the memory units that is physically adjacent to the first memory unit is obtained. In response to the FBC of the second memory unit exceeding a threshold, the second memory unit is refreshed.

Memory controller and memory system performing write disturbance management

Examples of present disclosure disclose a memory device and an operation method thereof, and a readable storage medium. The memory device includes: a first memory region and a second memory region, each including a plurality of memory cells; and a peripheral circuit coupled with the first memory region and the second memory region and configured to: when writing data to the first memory region, perform a first program operation on memory cells to be programmed in the first memory region by using first program voltages that increase gradually; and when writing data in the first memory region to the second memory region, perform a second program operation on memory cells to be programmed in the second memory region by using second program voltages that increase gradually.

Memory device, operation method thereof, and readable storage medium

According to one aspect, the present disclosure provides a decoder. The decoder may include a posterior probability storage module that stores a posterior probability message respectively corresponding to each of a plurality of cyclic permutation matrices. The decoder may include a node message storage module that stores a message transmitted to a variable node by a check node respectively corresponding to each of the plurality of cyclic permutation matrices. The decoder may include a message updating module that sequentially receives the posterior probability message and the message transmitted to the variable node by the check node respectively corresponding to each of the plurality of cyclic permutation matrices in a first order, and sequentially outputs the updated message transmitted to the variable node by the check node and an updated posterior probability message respectively corresponding to each of the plurality of cyclic permutation matrices in a second order.

Decoder, decoding method, memory controller, and memory system

Embodiments of the present disclosure disclose a memory system and operation method thereof, a memory controller and a memory. The memory system includes a memory. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, and m is a positive integer greater than 1. The operation method includes: determining, by the peripheral circuit, (n+1)th group of page data according to a received prefix command and received n groups of page data, wherein n is a positive integer, and n+1 is a positive integer less than or equal to m; and writing the n groups of page data and the (n+1)th group of page data into the memory cell array to generate 2different data states in the memory cell array.

Memory systems and operation methods thereof, memory controllers and memories

The present application discloses a memory, a memory system, and a method for operating memory, which belongs to the memory techniques field. The method for operating memory comprises determining a storage state of a reference memory cell, determining a discharge duration of a sensing node corresponding to a target memory cell based on the storage state of the reference memory cell, and reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell to obtain read results. The target memory cell and the reference memory cell are located in the same string and are adjacent, and the programming order of the reference memory cell is after that of the target memory cell. The present application may reduce the influence on reading memory cells by interlayer interference and improve the accuracy of reading memory cells.

Memory, a memory system, and a method for operating memory

In examples, a method of controlling a memory system comprises obtaining a first soft-bit data corresponding to a hard-bit data read from a memory and a first lookup table, where the first lookup table comprises a first log-likelihood ratio determined based on a first reference read voltage of the memory. The method comprises performing a first soft decoding operation according to the first log-likelihood ratio and the first soft-bit data. The method comprises performing at least one shift to the first log-likelihood ratio and performing a second soft decoding operation according to a log-likelihood ratio after each shift and the first soft-bit data when the first soft decoding operation is determined to have failed to decode.

Method for controlling a memory system, a memory system, and an electronic device

A memory controller coupled to a memory device including an array of memory cells, each memory cell being set to one of 2states corresponding to a piece of N-bits data, where N is an integer greater than 1, and the array of memory cells being partitioned into one or more units. The memory controller is coupled to the memory device and configured to, upon executing instructions, obtain, from the memory device, a number P of memory cells in a unit of the units that are in one or more programmed states of the 2states; calculate, based on the number P, a compensated read voltage with an offset from a default read voltage; and provide, to the memory device, the compensated read voltage for a read operation performed on a selected memory cell of the memory cells in a unit of the units.

Read offset compensation in read operation of memory device

An example memory controller and readable storage medium are disclosed. An example memory system includes: a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller is configured to: determine whether data for the logical block address mapping of a received read command belongs to tables of a first class or tables of a second class, and confirm the heat of the data corresponding to the logical block address of the received read command; determine a level of the amount of drift of a threshold voltage of a memory cell corresponding to the logical block address, according to the heat of the data corresponding to the logical block address of the received read command; determine different read voltages that are correspondingly sent to the memory cell corresponding to the logical block address, according to different levels of the amount of drift.

Memory systems and methods of operating thereof, memory controllers and readable storage media

According to one aspect of the present disclosure, a decoder is provided. The decoder may include a cache module. The cache module may be configured to cache soft data related to a codeword to be decoded. The decoder may include a flip-indication module. The flip-indication module may be configured to obtain the soft data from the cache module. The flip-indication module may be configured to, when performing hard-decision decoding on the codeword to be decoded, determine, at least in a first flip iteration and with assistance of the soft data, a number of parity checks not satisfied by bits in the codeword to be decoded.

The present disclosure involves methods, apparatuses, and computer-readable storage media for media scan in a memory system. In one example, a method for a memory system includes receiving commands from a host coupled to the memory system, wherein the memory system includes a memory device, the memory device includes a memory cell array, and the memory cell array includes a number of memory cells. The method further includes performing operations on the memory device based on the commands. The method further includes scanning at least a group of memory cells of the memory cell array by performing a number of scans within a scan period among the operations.

Media scan in memory systems

In certain aspects, a memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device. The non-volatile memory device includes a plurality of memory groups. Each of the memory groups includes a plurality of memory units. The memory controller is configured to perform at least one of a first wear-leveling process by swapping a first memory group of the memory groups and a second memory group of the memory groups based on a first group write count for the first memory group and a second group write count for the second memory group, or a second wear-leveling process by swapping a first memory unit of the memory units and a second memory unit of the memory units based on a first unit write count for the first memory unit and a second unit write count for the second memory unit.

Memory controller and memory system performing wear-leveling

The present disclosure provides a memory system with a non-volatile memory that includes a plurality of storage areas. Each storage may include a plurality of first storage groups in a first area and a plurality of second storage groups in a second area. The first area may support physical addressing. The second area may not support physical addressing. A memory controller of the memory system may perform a wear leveling process by swapping a first storage group having a first group write count with a second storage group having a second group write count. The first group write count may be a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups. The second group write count may be a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.

Memory system and method of operating thereof, and computer-readable storage medium

Aspects of the disclosure are directed to a memory system that can include a controller and a memory coupled thereto, each memory cell of the memory is configured to store m-bit information, and the controller includes at least one of an exclusive OR circuit, an inverter and an access circuit. The controller is configured to receive n groups of logic page data, and generate, at different values of m and n, at least one group of logic page data selectively by at least one of the exclusive OR circuit, the inverter and the access circuit. The controller is further configured to transmit the m groups of logic page data to the memory to generate 2n different data states in the memory.

Memory system controller, memory and operation methods thereof, and electronic device

Examples provide for error correction. The error correction includes: obtaining first soft data according to first hard read data and cached second hard read data after hard decision decoding for the first hard read data fails, wherein the first hard read data is read according to a first hard read voltage, and the second hard read data is read according to a second hard read voltage before reading the first hard read data; and performing first soft decision decoding according to the first soft data and the first hard read data, or according to the first soft data and the second hard read data, wherein the first hard read voltage is one of a plurality of re-read voltages corresponding to a read command; and the second hard read voltage is an initial read voltage or a re-read voltage of the plurality of re-read voltages except the first hard read voltage.

Error correction method, memory system and memory controller

The present disclosure provides a decoder including: a check node updating circuit and a variable node updating circuit. In a first time period, these circuits obtain the check node messages corresponding to different layers of the check matrix in the first updating units of different levels in the first updating units of α levels and obtain corresponding intermediate calculation values in the second updating units of different levels in the second updating units of α levels. After, the second updating units sequentially receive the check node messages corresponding to each layer of the check matrix and calculate the received check node messages with the intermediate calculation values of the second updating unit of the next level. From this, they obtain the variable node messages corresponding to different columns of the check matrix in the second updating units of different levels in the second updating units of α levels.

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Hubei, China

Hua Tan