Xilinx, Inc.

Alibaba Group Holding Limited

Hua Sun

Sundararajarao Mohan

L James Hwang

Vinod Kumar Kathail

Jorge Ernesto Carrillo

Yogesh Laxmikant Chobe

Jun Zheng

Tom Shui

Dengcheng Zhu

A method for automatically establishing an address-port mapping table of a switching device in an interconnect fabric uses hardware link-up and link-down processes to build and update the lowest cost (e.g., shortest path) port entries in the mapping table. Traffic loops are precluded by comparing cost values based on the source addresses of the devices in the interconnect fabric, without blocking any particular port.

Automatically establishing an address mapping table in a heterogeneous device interconnect fabric

A system is provided for controlling congestion. The system sends a first data packet to a destination device, and receives a first acknowledgement packet from the destination device corresponding to the first data packet. Next, the system can extract, from the first acknowledgement packet, a first pair of timestamp values which includes a first time stamp value generated by the source device and a second timestamp value generated by the destination device, and further extract, from a second acknowledgement packet corresponding to a subsequently transmitted packet to the destination device, a second pair of time stamp values which include a third time stamp value generated by the source device and a fourth time stamp value generated by the destination device. The system can determine the congestion change by calculating a one-way travel time difference based on the first pair of timestamp values with the second pair of timestamp values.

System and method for congestion control using time difference congestion notification

Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

Encapsulating metadata of a platform for application-specific tailoring and reuse of the platform in an integrated circuit

In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.

Compilation of system designs

Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.

Automatic implementation of a customized system-on-chip

In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.

Compilation of HLL code with hardware accelerated functions

Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.

Hardware and software cosynthesis performance estimation

A method of automatically developing a data transfer network includes determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit. The circuit design is specified in a high level programming language, and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit. Each of the plurality of data transfers is characterized. Each of the plurality of data transfers is correlated with resources of the target integrated circuit. A programmatic description of a data transfer network is generated for the circuit design. The data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.

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