Other

Siemens Aktiengesellschaft

International Business Machines Corporation

Infineon Technologies Ag

Xilinx, Inc.

Hua Shen

David Edward Kotecki

Jenny Lian

Satish D Athavale

Gerhard Kunkel

Laertis Economikos

Yun-Yu Wang

Rajarao Jammy

Martin Gutsche

Joachim Hoepfner

Chenting Lin

Carl John Radens

Yun Yu Wang

Stephen M Trimberger

Steven P Young

Katherine Lynn Saenger

Thomas J Shaw

Michael J Hart

Hiroyuki Akatsu

Robert B Laibowitz

John A Miller

Jingyu Lian

Andreas Knorr

Horatio Seymour Wildman

Ronald J Schutz

Daniel Gitlin

Philip L Flaitz

Fen Fen Jamin

Nirmal Chaudhary

Keith K Wong

Cheruvu Suryanarayana Murthy

Philip Edward Batson

Joachim Nuetzel

Nimal Chaudhary

Nicholas Nagel

Lee J Kimball

In accordance with the present invention, a method for forming a crystalline silicon nitride layer, includes the steps of providing a crystalline silicon substrate with an exposed surface, precleaning the exposed surface by employing a hydrogen prebake and exposing the exposed surface to nitrogen to form a crystalline silicon nitride layer. Also, a trench capacitor, in accordance with the present invention, includes a crystalline silicon substrate including deep trenches having surface substantially free of native oxide. A dielectric stack, including a crystalline silicon nitride layer, is formed on the sidewalls of the trenches. The dielectric stack forms a node dielectric between electrodes of the trench capacitor.

Method for forming crystalline silicon nitride

Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

Structures and methods for selectively applying a well bias to portions of a programmable device

An integrated circuit comprising a vertically oriented device formed with a substantially SELF ALIGNED process, in which the trench, active area (e.g., ), and gate (e.g., ) of a DRAM cell may be formed using a minimal number of masks and lithographic steps. Using this process, a DRAM cell comprising a vertical transistor and a buried word line (e.g., ) may be formed. A gate dielectric (e.g., ) may be disposed adjacent the active area, and the portion of the buried word line adjacent the gate dielectric may function as the vertically oriented gate for the vertical transistor. The DRAM memory cell may comprise one of a variety of capacitors, such a trench capacitor underlying the vertical transistor, or a stack capacitor (e.g., ) overlying the vertical transistor. When a stack capacitor is used, a buried bit line (e.g., ) underlying the vertical transistor may also be used.

Method of forming an integrated circuit comprising a self aligned trench

A method of forming an integrated barrier/contact for stacked capacitors is provided which results in reduced cost of ownership and in a barrier which is nominally several times thicker than convention structures. The resulting structure results in decreased contact plug resistance as compared with conventional devices.

Method for forming an integrated barrier/plug for a stacked capacitor

In semiconductor dynamic random access memory circuits using stacked capacitor storage elements formed using high permittivity dielectric material, it is typical to form the stacked capacitors using noble metal electrodes. Typically, the etching process for the noble metal electrodes requires the use of a hard mask patterning material such as silicon oxide. Removal of this hard mask frequently results in damage to the dielectric surface surrounding the patterned noble metal electrode. A method of removing the hard mask material without damaging the surrounding surface includes the steps of: depositing a soft mask photoresist material over the composite surface, including the hard masked covered noble metal electrode and the dielectric surface, in a manner such that the soft mask material is thinner over the region of the noble metal electrode; removing the portion of the soft mask material over the noble metal electrode leaving the soft mask material over the dielectric surface; etching the hard mask material with the soft mask material protecting the dielectric surface; and removing the remaining portion of the soft mask material.

Method for removal of hard mask used to define noble metal electrode

A process and solution for selectively wet etching a titanium based perovskite material disposed on a silicon oxide or silicon nitride substrate is disclosed herein. The solution is composed of hydrogen peroxide, an acid and deionized water. The solution is heated to a temperature between 25 and 90 degrees Celsius. The titanium based perovskite material may be barium strontium titanate, barium titanate, strontium titanate or a lead titanate. The solution selectively etches the perovskite material while the substrate is only minimally etched, if at all. The process and solution allows for an etching rate up to thirty times greater than conventional etching rates for similar perovskite materials selective to various substrate, barrier and mask layers, including SiO .

Hydrogen peroxide and acid etchant for a wet etch process

A method for forming an electrode. The method includes forming a conductive plug through a first dielectric layer. The plug extends from an upper surface of the first dielectric layer to a contact region in a semiconductor substrate. The electrode is formed photolithographically, misalignment of a mask registration in the photolithography resulting in exposing surface portions of the barrier contact. A second dielectric layer is deposited over the first dielectric layer, over side portions and top portions of the formed electrode, and over the exposed portions of barrier contact. A sacrificial material is provided on portions of the second dielectric layer disposed on lower sides of the, electrode, on portions of the second dielectric layer disposed on the first dielectric layer, and on said exposed portions of the barrier contact while exposing portions of the second dielectric layer on the top portions and upper side portions of the formed electrode. The exposed portions of the second dielectric layer are removed while leaving the portions of the second dielectric layer on the exposed portions of the barrier contact. A material is deposited over exposed portions of the first electrode and over remaining portions of the second dielectric layer in an oxidizing environment. A second electrode is formed for the storage element over the material. In forming a capacitor storage element, the portion of the second dielectric layer on the barrier contact prevents oxidation of the barrier contact during the material formation process.

Semiconductor structure and manufacturing method

A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.

Capacitor stack structure and method of fabricating description

The present invention includes a method of improving conductivity between an electrode and a plug in a stacked capacitor where an oxide has formed therebetween. The method includes the steps of bombarding the oxide with ions and mixing the oxide with materials of the electrode and the plug to increase a conductivity between the electrode and the plug. A method of forming a diffusion barrier within an electrode in a stacked capacitor includes the steps of providing a stacked capacitor having a plug coupled to an electrode and bombarding the electrode with ions to form the diffusion barrier within the electrode such that the diffusion barrier is electrically conductive. A stacked capacitor in accordance with the present invention includes an electrode, a plug for electrically accessing a storage node, the plug being coupled to the electrode and a barrier layer disposed within the electrode for preventing diffusion of materials which reduce conductivity between the electrode and the plug.

Stack capacitor with improved plug conductivity

A method for forming a patterned shape from a noble metal, in accordance with the present invention, includes forming a noble metal layer over a dielectric layer and patterning a hard mask layer on the noble metal layer. The hard mask layer includes a mask material that is selectively removable relative to the noble metal layer and the dielectric layer and capable of withstanding plasma etching. Alternately, the hard mask material may be consumable during the noble metal layer plasma etching. Plasma etching is performed on the noble metal layer in accordance with the patterned hard mask layer. The hard mask layer is removed such that a patterned shape formed in the noble metal layer remains intact after the plasma etching and the hard mask removal.

Easy to remove hard mask layer for semiconductor device fabrication

A method for forming a dielectric layer includes exposing a surface to a first dielectric material in gaseous form at a first temperature. Nuclei of the first dielectric material are formed on the surface. A layer of a second dielectric material is deposited on the surface by employing the nuclei as seeds for layer growth wherein the depositing is performed at a second temperature which is greater than the first temperature.

High dielectric constant material deposition to achieve high capacitance

A method for forming a stacked capacitor includes the steps of providing a first insulating layer having a conductive access path therethrough, forming a second insulating layer on the first insulating layer, forming a trench in the second insulating layer, the trench having tapered sidewalls, forming a first electrode in the trench and on the trench sidewalls, the first electrode being electrically coupled to the conductive access path, forming a dielectric layer on the first electrode and forming a second electrode on the dielectric layer. A stacked capacitor having increased surface area includes a first electrode formed in a trench provided in a dielectric material. The first electrode has tapered surfaces forming a conically shaped portion of the first electrode, the first electrode for accessing a capacitively coupled storage node.

Tapered electrode for stacked capacitors

A memory cell includes a field effect transistor and a stacked capacitor. The stacked capacitor has one plate formed by a platinum layer over the side walls of a portion of a dielectric layer that overlies a conductive layer that makes contact to a conductive plug connected to the storage node of the cell. The capacitor dielectric overlies the sidewalls and top of the dielectric layer portion and the other plate of the capacitor is formed by a platinum layer over the capacitor dielectric.

Stacked capacitator memory cell and method of fabrication

Doped semiconductor with high dopant concentrations in small semiconductor regions without excess spreading of the doped region are formed by:

Low temperature diffusion process for dopant concentration enhancement

Method of forming stack capacitor with improved plug conductivity

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Beacon, NY, United States of America

Hua Shen