Alpha Omega Semiconductor Inc.

Molex Corporation

Baoshan Iron & Steel Co., Ltd.

Alpha and Omega Semiconductor (cayman) Ltd.

Chipmos Technologies (bermuda) Ltd

Chipmos Technologies (shanghai) Ltd.

Hua Pan

Jun Lu

Ming-Chen Lu

Zhiqiang Niu

Yan Huo

You-Xiang Zheng

Hamza Yilmaz

Yueh-Se Ho

Lei Shi

Xiaotian Zhang

Ming Lei

Haomin Jiang

Yan Xun Xue

Yue Wu

Hongtao Gao

Jianxin Ye

Yongchao Su

Jie-Hung Chiou

Guo Feng Lian

Chih-Lung Huang

Dungui Zuo

Chengjie Liu

Zhongqu Sun

A first electrical connector, a second electrical connector and an electrical connector assembly are provided. The first electrical connector includes: a first connector housing including a main body, a locking mechanism which extend forwardly from an upper surface of the main body and a plurality of mating posts which extend forwardly a front surface of the main body, each mating post is interiorly formed with a first terminal receiving cavity which penetrates in a front-rear direction, a first prevent mis-insertion protruding rib protrudes from a middle portion of at least one of the mating posts, and a second prevent mis-insertion protruding rib protrudes from a side edge of at least one of the mating posts; and a plurality of first conductive terminals which are correspondingly inserted into mating posts, each first conductive terminal comprises a first mating portion which is received in the corresponding first terminal receiving cavity and a first tail portion which is positioned behind the first mating portion. It facilitates correct mating between the first electrical connector and the second electrical connector.

First electrical connector, second electrical connector and electrical connector assembly

Electrical connector

A resistance spot welding method of galvanized high-strength steel with good joint performance, in which three welding pulses are used within one spot welding schedule. The method includes applying a first welding pulse and a second welding pulse which are used for generating a nugget and suppressing the generation of liquid metal embrittlement (LME) cracks, respectively. The first welding pulse generates a nugget having a diameter of 3.75T-4.25Tin which T represents a plate thickness. The second welding pulse causes the nugget to grow at a rate less than a rate of growth during the first welding pulse. A third welding pulse, which is a tempering pulse, is applied for improving plasticity of a welding spot.

Method of resistance spot welding of galvanized high-strength steel with good joint performance

Provided is a steel welding component having a steel welding blank with an aluminum or aluminum alloy coating. The welding blank is composed of a steel substrate and coatings comprising an intermetallic compound alloy layer contacting the substrate, and a metal alloy layer on the intermetallic compound alloy layer. On at least one of the coating surfaces of the welding blank, the coating within an area to be welded has been totally removed, and an end face of the coating on the side of the coating within the area to be welded removed has an angle of &#x3b2; being 0-80&#xb0; with a plane vertical to a surface of the substrate which is parallel to the welding seam. Also provided are welding methods for the steel welding component. The steel welding blank provided ensures the tensile strength, elongation, and corrosion resistance of a hot-stamped welded joint.

Steel welding component with aluminum or aluminum alloy coating, and preparation method therefor

A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.

Power semiconductor device with small contact footprint and the preparation method

A method of manufacturing an embedded package comprises attaching a plurality of chips on a pre-mold lead frame; forming a first lamination layer on the plurality of chips, the pre-mold lead frame and a plurality of pins; forming a first plurality of vias and a second plurality of vias through the first lamination layer; forming a respective conductive plug of a plurality of conductive plugs by depositing a respective conductive material in each of the first plurality of vias and each of the second plurality of vias; and electrically connecting the plurality of conductive plugs on the electrodes of the plurality of chips to the plurality of conductive plugs on the plurality of pins.

Embedded package and method thereof

The present invention discloses a new embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, so that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect an electrode of a chip to a corresponding pin or to connect the chips together. The new embedded package of the invention with a three-dimensional stack capacity improves the thickness, thermal and electrical properties and the flexible power and logic hybrid design.

A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the metal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

Method of making stacked multi-chip packaging structure

A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

Stacked multi-chip packaging structure and manufacturing method thereof

A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air.

Aluminum alloy lead-frame and its use in fabrication of power semiconductor package

A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface and chip bonding pads disposed thereon. The lead frame is fixed on the chip and the lead frame includes inner leads, at least one bus bar, an insulating layer and transfer bonding pads. The bus bar is located between the chip bonding pads and the inner leads. The insulating layer is disposed on the bus bar and the transfer bonding pads are disposed thereon. The inner leads and the bus bar are located above the active surface. The chip and the insulating layer are located respectively on two opposite surfaces of the bus bar. The first bonding wires respectively connect the chip bonding pads and the transfer bonding pads. The second bonding wires respectively connect the transfer bonding pads and the inner leads.

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Shanghai, China

Hua Pan