Utac Headquarters Pte. Ltd.

Utac - United Test and Assembly Test Center Ltd.

Hua Hong Tan

Kriangsak Sae Le

Wedanni Linsangan Micla

Rui Huang

Nathapong Suthiwongsunthorn

Roel Adeva Robles

Antonio Jr Bambalan Dimaano

Beng Yeung Ho

Nelson Agbisit De Vera

Saravuth Sirinorakul

Paweena Phatto

Thanawat Jaengkrajarng

Wilson Poh Leng Ong

Tanawan Chaowasakoo

Somsak Phukronghin

Alexander Lucero Laylo

Hien Boon Tan

Anthony Yi Sheng Sun

Chuen Khiang Wang

Chee Kay Chow

Teddy Joaquin Carreon

Enrique Jr Sarile

Dennis Fernandez Tresnado

Wing Keung Lam

Yao Hong Wu

Tao Hu

Zong Xiang Cai

Antonino Ii Milanes

Wei Ming Xian

Albert Louis Bove

Mario Arwin Fabian

Ming Koon Ang

Thian Hwee Tan

Mauro Jr Dionisio

Sin Nee Song

Steven Yu Feng Yao

Kian Soo Lim

Aaron Lyn Foong Tan

A semiconductor manufacturing equipment cleaning system has a multi-station cleaning and inspection system. Within semiconductor manufacturing equipment cleaning system, a tray cleaning station uses a first rotating brush passing over a first surface of a carrier and possibly semiconductor die, and a second rotating brush passing over a second surface of the carrier and semiconductor die opposite the first surface of the carrier and semiconductor die. Debris and contaminants dislodged from the first surface and second surface of the carrier by the first rotating brush and second rotating brush are removed under vacuum suction. A conveyor transports the carrier through the multi-station cleaning and inspection system. The first rotating brush and second rotating brush move in tandem across the first surface and second surface of the carrier. Air pressure is injected across the first rotating brush and second rotating brush to further remove debris and contaminants.

System and method of cleaning and inspecting semiconductor die carrier

An embodiment related to a device. The device includes a first die with first and second die surfaces. The second die surface is bonded to a first die attach pad (DAP) disposed on a first substrate surface of a package substrate and the first die surface includes a first die contact pad. The device also includes a first clip bond including a first clip bond horizontal planar portion attached to the first die contact pad on the first die surface, and a first clip bond vertical portion disposed on an edge of the first clip bond horizontal planar portion. The first clip bond vertical portion is attached to a first substrate bond pad on the first substrate surface. The device further includes a first conductive clip-die bonding layer with spacers on the first die contact pad of the first die. The first conductive clip-die bonding layer bonds the first clip bond horizontal planar portion to the first die contact pad, and the spacers maintain a uniform Bond Line Thickness (BLT) of the first conductive clip-die bonding layer.

Semiconductor packages and methods of packaging semiconductor devices

The present disclosure is directed to a high throughput clip bonding tool or system which is flexible and easily adapts to different clip bond pitches or sizes. The clip bonding system may be an integrated system with various modules, including a clip singulation module, a feeder module, a transfer module and a clip attach module within a shared footprint. For example, an incoming clip source may be fed to the clip singulation module for clip singulation before the singulated clips are transferred by the feeder and transfer modules to a clip presentation area for clip alignment before pickup. A pickup tool of the clip attach module is configured to facilitate pickup and attachment of clips onto the semiconductor packages to be clip bonded. For example, the pickup head is programmable to facilitate clip bonding process of different applications which may require clips and packages with different sizes.

Clip bond semiconductor packages and assembly tools

A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed. The discontinuity enhances adhesion of the encapsulant to the protective cover.

Reliable semiconductor packages

An embodiment related to a method for forming a device is disclosed. The method includes providing a package substrate having a first die attach pad (DAP) and a first bond pad, forming a first conductive die-substrate bonding layer on the first DAP, and attaching a first major surface of a first die to the first DAP. The first die includes a first die contact pad on a second major surface of the first die. A first conductive clip-die bonding layer with spacers is formed on the first die contact pad of the first die. A first conductive clip-substrate bonding layer is formed on the first bond pad of the package substrate. The method also includes attaching a first clip bond to the first die and the first bond pad. The first clip bond includes a first horizontal planar portion attached to the first die over the first die contact pad and a second vertical portion attached to the first bond pad.

Conductive bonding layer with spacers between a package substrate and chip

A method for forming a semiconductor package is disclosed herein. The method includes forming a package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate includes a recess region below the first major surface defined with a die region and a non-die region surrounding the die region. A semiconductor die is disposed in the die region within the recess region. A dam structure is disposed within the recess region. The dam structure surrounds the semiconductor die and extends upwardly to a height below the first major surface of the package substrate. The method also includes dispensing a liquid encapsulant material into the recess region. The liquid encapsulant material is surrounded by the dam structure and extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.

Cavity wall structure for semiconductor packaging

An improved method for forming a semiconductor package is disclosed herein. The method includes forming a multi-layer package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region. A semiconductor die is attached to the die region within the recess region. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.

Semiconductor chip package and method of manufacture

Growing community of inventors

Singapore, Singapore

Hua Hong Tan