Qualcomm Incorporated

Hua Guan

Ngai Yeung Ho

Jize Jiang

Kan Li

Kuan Chuang Koay

Chi Fan Yung

Vincenzo Peluso

Liangguo Shen

Fan Yang

Mengmeng Du

YuFei Pan

Todd Robert Sutton

Chunlei Shi

Guolei Yu

Xiaodan Zou

Cheong Kun

Sandeep Chaman Dhar

Hardik M Patel

Eric B Zeisel

Baiying Yu

Shamim Ahmed

Nihit Bajaj

Chengyue Yu

Qi Lou

Loai Galal Bahgat Salem

Xiaodong Meng

Yingjie Chen

An apparatus is disclosed for adaptive switch driving. In an example aspect, the apparatus includes a switching circuit configured to selectively be in a first state that provides an input voltage as an output voltage, be in a second state that provides a ground voltage as the output voltage, or be in a third state that causes the output voltage to change from the input voltage to the ground voltage according to a slew rate. The third state enables the switching circuit to transition from the first state to the second state. The switching circuit is also configured to adjust the slew rate of the output voltage for the third state responsive to at least one of the following: a change in a magnitude of a direct-current supply voltage or a change in a magnitude of an input current.

Adaptive switch driving

In certain aspects, a system includes an amplifying circuit having an input and an output, a high-pass filter coupled between a gate of a pass transistor of a low dropout (LDO) regulator and the input of the amplifying circuit, and a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the gate of the pass transistor.

Power supply rejection enhancer

A power supply circuit and techniques for voltage regulation are described. Certain aspects provide a method of supplying power by a power supply circuit. The method generally includes: generating an output voltage based on a voltage at a Vin node via a first transistor having a gate coupled to a gate of a second transistor, wherein a source of the second transistor is coupled to the Vin node and wherein a drain of the second transistor is coupled a drain of a third transistor; and sourcing a current to the third transistor, wherein during a light load condition of the power supply circuit, the current varies based on the voltage at a Vout node of the power supply circuit, and during a heavy load condition of the power supply circuit, the current is limited based on a current threshold.

Nonlinear current mirror for fast transient and low power regulator

Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.

Integrated circuit package with internal circuitry to detect external component parameters and parasitics

The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.

Low-dropout (LDO) voltage regulator with voltage droop compensation circuit

In certain aspects, a system includes an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.

Certain aspects of the present disclosure provide a power supply system. The power supply system generally includes a first voltage regulator and a second voltage regulator, outputs of the first voltage regulator and the second voltage regulator being coupled to an output of the power supply system. The power supply system may also include a current balancer circuit configured to adjust an output current of the first voltage regulator based on determined headrooms of the first voltage regulator and the second voltage regulator.

Load balancing architecture for ganging voltage regulators

Aspects of the present disclosure provide a voltage reference architecture. An example circuit generally includes a resistor ladder, a reference current source, and a plurality of multiplexers. The resistor ladder comprises a plurality of resistive elements coupled in series. The reference current source has an output coupled to the resistor ladder. The plurality of multiplexers have inputs coupled to one or more nodes between the plurality of resistive elements and the output of the reference current source, each of the multiplexers having an output selectively coupled to one of the inputs of the multiplexer.

Voltage reference architecture

An LDO regulator is provided that includes a bias circuit that generates a bias current having a non-linear relationship to an output current for the LDO regulator. The LDO regulator is also configured to clamp the output current.

Low dropout regulator with non-linear biasing and current clamping circuit

Certain aspects of the present disclosure generally relate a regulator. For example, the regulator may include a control stage, a sense capacitor having first and second terminals, the first terminal coupled to an output of the voltage regulator, and a current amplifier having an input coupled to the second terminal of the sense capacitor and an output coupled to the control stage. The control stage of the regulator may adjust the output voltage of the regulator based at least in part on a current generated by the current amplifier.

Methods and apparatus for voltage regulation using output sense current

Circuit techniques control multiple regulator circuits. Regulator circuits are configured to time share voltage control circuitry. The voltage control circuitry may include multiple sets of switches to selectively couple a voltage control circuit with a selected voltage regulation loop of one of the regulators.

Multiple input multiple output regulator controller system

Certain aspects of the present disclosure provide methods and apparatus for implementing a voltage regulator. The voltage regulator includes a power field effect transistor (FET) comprising a gate terminal. The voltage regulator further includes a charge pump, the charge pump comprising a capacitor switchably coupled to the gate terminal. The voltage regulator further includes a current outputting amplifier switchably coupled to the capacitor.

Embedded charge pump voltage regulator

An integrated circuit is disclosed for current-controlled voltage regulation. In an example aspect, the integrated circuit includes a voltage regulator and a current-controlled clamp. The voltage regulator has a regulator output node and produces a regulator current. The voltage regulator includes an error amplifier and an output transistor. The error amplifier has first and second input nodes and an error amplifier output node, with the first input node coupled to a reference voltage. The error amplifier generates an error amplifier output voltage at the output node. The output transistor is coupled between the error amplifier output node and the regulator output node. The output transistor is coupled to the second input node via the regulator output node to establish a feedback path for the voltage regulator. The current-controlled clamp is coupled to the error amplifier output node and clamps the error amplifier output voltage based on the regulator current.

Current-controlled voltage regulation

A voltage regulator having current sense capability may include an input node and an output node. A first output device may be electrically connected between the input node and the output node, and configured to control current flow through the first output device to regulate a voltage at the output node. A current sense circuit may be configured to produce a signal that is indicative of the current through the first output device. The current sense circuit may be configured to perform a first kind of offset compensation operation to reduce an offset voltage in an error amplifier of the current sense circuit, and to perform a second kind of offset compensation operation to reduce the offset voltage in the error amplifier.

Growing community of inventors

San Diego, CA, United States of America

Hua Guan