University of Electronic Science and Technology of China

Hua Fan

Quanyuan Feng

Yuanjun Cen

Huaying Su

Dagang Li

Daqian Hu

Franco Maloberti

Hadi Heidari

Jing Luo

Yilin Liu

Huichao Yue

Panfeng Zhao

Guosong Wang

Chen Wang

Wei Zhang

Dainan Zhang

Shaoqing Lu

Jingxuan Yang

Jingtao Li

Qianqian Deng

Peng Lei

Kai Xu

Lang Feng

Xiaopeng Diao

Xiaohu Qi

Yiming Hu

Guo Li

Kelin Zhang

Disclosed is a three-axis Hall angle sensor with an accuracy of 0.3°. The sensor is mainly designed by means of finite element software and COMSOL Multiphysics. The present specification will be mainly performed in three steps. In the first step, a cross-shape horizontal Hall element for measuring the magnetic field in the vertical direction, that is, the direction z, is studied. The second section mainly studies a three-contact four-Hall vertical element for measuring the magnetic field in the directions x, y. The third part is to design the angle sensor. Compared with the horizontal Hall element, the vertical Hall element has a relatively large offset, therefore, four vertical Hall elements are used to measure the magnetic field in the horizontal direction, and two complementary vertical structures are used to eliminate the error when the magnetic field in the same horizontal direction is measured.

Three-axis Hall angle sensor with accuracy of 0.3°

The present disclosure relates to the field of microelectronics and solid-state electronics, and in particular to a calibration system and method for weighting errors brought about by parasitic capacitance in split capacitor-based successive approximation analog-to-digital converters. The method uses an MSB array that does not add additional capacitors, only a switch Sto reduce the comparator design difficulty. Meanwhile, an LSB array may add a calibration DAC array Cincluding a binary array of P-bit unit capacitors, a calibration structure C, and a ground switch S. The calibration structure Cincludes four unit capacitors and two switches Sand S. By controlling the switches Sand Sdifferent capacitance values can be generated to reduce the chip area consumption. This structure can reduce the error to LSB/4 and the weighting error of the ADC, and increases the effective number of bits of the ADC without excessively increasing comparator gain.

System and method for calibrating weighting errors in split capacitance successive approximation analog-to-digital converters

A DC-DC converter circuit with selectable working modes is disclosed. Compared with the traditional chip that works in one mode, the DC-DC converter with selectable working modes adds only a mode selection circuit, so that the chip can work in voltage control mode or current control mode. On the one hand, the applications of the chip are more extensive, and on the other hand, when the applications are different, the cost of developing a DC-DC converter with selectable working mode is greatly reduced compared with the traditional DC-DC converter.

DC-DC converter with selectable working mode

A voltage-to-time converter (VTC) for a time-domain analog-to-digital converter is disclosed, which provides a time-domain analog-to-digital converter (T-ADC) with low power consumption and high precision. By combining the advantages of current-starving technology, current mirror technology, and body biasing technology, compared with the traditional structure, the VTC and T-ADC achieve excellent performance, such as low power consumption, high linearity, wide input dynamic range, and strong anti-interference to PVT variations. Compared with the traditional voltage-to-time converter, the disclosed voltage-to-time converter has a wider input dynamic range and higher linearity. The input voltage is connected to transistors in the circuit as a body bias, resulting in a very small body current, and no apparent increase in power consumption. The design of a low-power voltage-to-time converter is realized.

Voltage-to-time converter architecture for time-domain analog-to-digital converter

A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors C*, C* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR ADC.

Method of calibrating capacitive array of successive approximation register analog-to-digital converter

A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C-C; and 4) selecting 64 groups of capacitors from Cto C, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.

Method for improving spurious free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) of capacitor-resistor combined successive approximation register (SAR) analog-to-digital converter (ADC) by capacitor re-configuration

A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.

Method of arranging capacitor array of successive approximation register analog-to-digital converter

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Chengdu, China

Hua Fan