Sigmastar Technology Ltd.

Mstar Semiconductor, Inc.

Genentech, Inc.

Hu He

Wei Zhu

Wenge Zhong

Xiaotian Zhu

Fei Zhang

Cheng-Wei Zheng

Zhilong Hu

Mingyong Sun

Lu Gao

Shi-Jie Zhou

An intelligent processing device includes a first memory, a second memory, a memory management circuit and a convolution operation circuit. The memory management circuit transfers an input data from an external memory to the first memory. The convolution operation circuit reads the input data from the first memory, and performs multiple stages of calculations to generate multiple sets of feature map data. After a first data tile of a first feature map data is generated, the memory management circuit stores the first data tile to the second memory. When a data amount of the first data tile stored satisfies a predetermined value, the memory management circuit transfers the first data tile from the second memory to the first memory, and the convolution operation circuit reads the first data tile from the first memory and accordingly performs a second-stage calculation to generate a second data tile of a second feature map data.

Intelligence processor device and method for reducing memory bandwidth

The invention provides a compound represented by the either of the following structural formulas, or a pharmaceutically acceptable salt, or a stereoisomer thereof, useful for treating cancer.

CDK inhibitors

An image processing device performs a filtering operation on image data according to a set of filter data, and includes a data reconstruction circuit, a memory and an intelligent processor. The data reconstruction circuit reconstructs data of blocks in the image data to generate first reconstruction data, and reconstructs the set of filter data to generate second reconstruction data. The memory stores the first reconstruction data and the second reconstruction data. The intelligent processor executes a depthwise convolution operation according to the first reconstruction data and the second reconstruction data to generate feature map data. Two adjacent of the multiple blocks have partially same data, and quantities of columns in the second reconstruction data are associated with a channel count of the depthwise convolution operation.

Image processing device and image processing method

A data dividing method applied to a computing device that performs a convolution operation based on an input image data and a weight data is provided. The method includes: determining a restriction condition in connection with the performing of the convolution operation by the computing device; determining a set of candidate data blocks for the input image data and a set of candidate data blocks for the weight data according to the restriction condition; generating an evaluation result by evaluating, according to candidate data blocks in the set of candidate data blocks for the input image data and the set of candidate data blocks for the weight data, an amount of data load of the computing device in accessing both an external memory and an internal memory of the computing device; and determining a method of dividing the input image data and the weight data according to the evaluation result.

Data dividing method and processor for convolution operation

A method for managing an image memory in an embedded device is provided. A node is obtained from a linked list of the image memory. It is judged whether valid data is present in a memory block corresponding to the node. When no valid data is present, it is judged whether valid data is present in a memory block corresponding to a previous node of the node. When valid data is present in the previous node, it is further judged whether the valid data is movable. When the valid data is movable, memory block information described in the two nodes is exchanged, and the valid data previously stored in the memory block corresponding to the previous node is moved to the memory block corresponding to the node.

Method and apparatus for managing video memory in embedded device

A method for loading a resource file for a game engine is provided. The method includes: activating a thread to a preload a predetermined resource file, wherein the predetermined resource file includes a texture resource file, and one or both of a structure resource file and a model resource file; and accessing and loading one or both of the structure resource file and the model resource file through memory mapping. The provided method increases a loading speed while loading a game resource file and fully utilizes computer resources.

Growing community of inventors

Shanghai, China

Hu He