International Business Machines Corporation

Hu H Chao

Jung H Chang

Feng-Hsien W Shih

Robert H Dennard

Nicky C Lu

Donelli J DiMaria

Jung-Herng Chang

A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal distribution tree of each integrated circuit. Phase comparison of signals produced by each clock distribution circuit tree provides a control signal for controlling the delay of a clock signal applied to a respective clock distribution tree. A gating circuit is disclosed which produces, in response to each clock signal produced by the clock distribution trees, an accurately controlled LOAD ENABLE and OUTPUT ENABLE signal.

System for reducing phase difference between clock signals of integrated

Single phase clock distribution circuit for providing clock signals to

An apparatus for correcting a faulty microcode contained in a control store of a microprogrammed processor. The apparatus comprises two functional parts; namely, the detection circuit for detecting operational codes that correspond to faulty microinstructions in the main control store ROM of the system and a programmable array which is used as the storage area for substitute microinstructions. The detection circuit is a circuit which operates as a logic NOR circuit and is utilized to detect valid operational codes of macroinstructions that correspond to microcode sequences that contain errors or faults. The programmable array consists of two loadable RAM's which contain error free microcode to replace the faulty microcode. The detection and correction occurs in parallel with the instruction decoding so that it does not have any impact on system cycle time.

Small programmable array to the on-chip control store for microcode

A single error correction, double error detection function for cache memories does not affect the normal cache access time the addition of the ECC function. Check bits are provided for multiple bytes of data, thereby lowering the overhead of the error detecting and correcting technique. When a single error is detected, a cycle is inserted by the control circuitry of the cache chip. At the same time, the clocks for the CPU are held high until released by the cache chip on the next cycle. Error correction on multi-byte data is performed using the 72/64 Hamming code. The technique requires a 2-port cache array (one write port, and one read port). However, the density of a true 2-port array is too low; therefore, the technique is implemented with a 1-port array using a time multiplexing technique, providing an effective 2-port array but with the density of a single port array.

Pipelined error checking and correction for cache memories

A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters is used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two-way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock. A high performance decoder circuit is provided in combination with the aforesaid CMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial.

Boost word-line clock and decoder-driver circuits in semiconductor

Word line CMOS decoder and driver circuits for semiconductor memories wherein the pitch of the decoder is twice that of the word line, the number of decoders required is reduced by a half, and the word line selection pulse can be applied prior to word line selection. The decoder and driver circuits include a transistor clock load device having its gate electrode driven by a decoder clock pulse or address pulse and a plurality of decoder address switch devices having their gate electrodes driven, respectively, by a plurality of address signals. The clock load device and the address switch devices are connected to a common node at the input to an inverter stage.

Word line decoder and driver circuits for high density semiconductor

MOS semiconductor address buffer for converting TTL logic states to a MOS logic state requiring only a single clock and having improved power efficiency. The address buffer operates in response to the single clock pulse to set a latch and connect the latch to output drives for providing complementary MOS logic levels.

High speed low power MOS buffer circuit for converting TTL logic signal

A process for providing different insulator systems for the storage capacitor and the FET in a single polysilicon one-device memory cell, such as a dynamic RAM cell, without requiring an additional masking level. In particular, the Hi-C or diffusion store ion implantation mask is used to implement this feature. This process can be used to provide different materials in the insulator system of the storage capacitor and the FET, or the same materials with different thicknesses.

Storage capacitor optimization for one device FET dynamic RAM cell

This invention provides improved non-volatile semiconductor memories which include a one device dynamic volatile memory circuit having a switching device, a storage capacitor and a non-volatile floating gate device disposed between the storage node and the switching device. The non-volatile floating gate device has a floating gate, a floating gate FET, a control gate and a voltage divider having first and second serially-connected capacitors, with the floating gate being disposed at the common point between the first and second capacitors. One of the capacitors includes a dual charge or electron injector structure and the capacitance of this capacitor has a value substantially less than that of the other capacitor.

Non-volatile dynamic RAM cell

A one-device, FET dynamic random access memory array is disclosed wherein a problem arising from the short-channel effect is reduced in single-polysilicon, one-device field effect transistor dynamic random access memory arrays where a portion of a word line is used as an electrode of a memory cell storage capacitor. When such word lines are accessed, boosted voltages can appear across the source-drain of FET devices of unaccessed memory cells causing them to conduct and spuriously lose information. This problem is minimized in such memory arrays by opening a pair of bit line switches so that the potential on an unselected bit line remains at the potential to which it was precharged. In this manner, the potential difference across the source-drain of the FETs of unselected memory cells can never exceed the potential to which all the bit lines are precharged.

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Pleasantville, NY, United States of America

Hu H Chao