Synopsys, Inc.

Hu Cai

Jun Wang

Cheng-Ming Wu

Jun Lu

Jun Zhu

Dick Liu

Randy Bishop

Jingyu Xu

Yuting Fu

Yun-Jui Li

Hwei-Tseng Wang

Sui Zheng

Yu Fan Lu

Jeong-Tyng Li

Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers. Next, a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool can be generated. Parasitic extraction on the IC design layout then be performed by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.

Extensible layer mapping for in-design verification

Techniques for analyzing a routed interconnection of a net of a circuit are discussed herein. Some embodiments may include a method comprising with a computer, analyzing the circuit to determine a performance parameter of the net, wherein the circuit is analyzed based at least in part on applying pre-layout simulation data of the net to layout data of the circuit. Additionally or alternatively, the circuit may be analyzed based on extracting characteristics of the routed interconnection from the layout data of the net.

In-design real-time electrical impact verification flow

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Shanghai, China

Hu Cai