Xilinx, Inc.

Xilinix, Inc.

Hsung Jai Im

Sunhom Paak

Boon Yong Ang

Raymond C Pang

Daniel Gitlin

Kevin Zheng

Stanley Yuanshih Chen

Vassili Kireev

Hongtao Zhang

Winson Lin

Kwansuhk Oh

Ankur Jain

Chuen-Huei Chou

Parag Upadhyaya

Jan Lodewijk De Jong

Patrick J Crotty

Kee Hian Tan

Henley Liu

David A Freitas

Jae-Gyung Ahn

Ronan Sean Casey

Jinyung Namkoong

Wenfeng Zhang

Nakul Narang

Jaeduk Han

Serhii Tumakha

Tony Le

Arianne B Roldan

Scott D McLeod

Yi Zhuang

Haritha Eachempatti

Yanfei Chen

Scott D Mcleod

Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.

DTC nonlinearity correction

Embodiments herein describe normalizing an output of a TDC in a DPLL to a resolution of the TDC. A DTC can delay a reference clock which is then input into the TDC. The TDC outputs a digital code indicating a time difference between the delayed reference clock output by the DTC and a clock generated by a DCO in the DPLL. This digital code is normalized to a resolution of the TDC and the result is filtered by a DLF.

DPLL timing normalization

Examples herein relate to electronic devices that include an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that implements timing adjustment based on output statistics. In an example, an electronic device includes an asynchronous SAR ADC, a statistics monitor, and an operation setting circuit. The asynchronous SAR ADC is configured to output output data. The statistics monitor is configured to capture samples at a bit position of the output data. The statistics monitor is further configured to generate an operational setting based on the captured samples. The operation setting circuit is configured to adjust an operating condition of the asynchronous SAR ADC based on the operational setting.

Asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) timing adjustment based on output statistics

A continuous time linear equalizer (CTLE) is disclosed. The CTLE may include a first cell configured to buffer and invert an input signal and generate a first intermediate signal, a second cell configured to buffer and invert the input signal and generate a second intermediate signal, and a first frequency section configured to selectively buffer and invert a first range of frequencies of the second intermediate signal. The first frequency section may include a first tunable resistor configured to provide a first resistance and a third cell coupled to the first tunable resistor configured to generate a third intermediate signal based on the first resistance.

CMOS analog circuits having a triode-based active load

An analog signal buffer is disclosed. The analog signal buffer may include a transconductance cell and an active load. The active load may load the current from the transconductance cell with a PMOS transistor and an NMOS transistor and provide a feedback resistance. A transimpedance amplifier is disclosed. The transimpedance amplifier may include a first cell configured to receive a first signal and output a second signal and a second cell coupled to the first cell. The second cell may include an active feedback structure configured to couple an output of the second cell to an input of the second cell.

A speculative decision feedback equalizer with split unroll multiplexers is provided. The speculative decision feedback equalizer splits an unroll multiplexer into two multiplexers. One split multiplexer provides a data path for the unroll selection signal, and the other split multiplexer provides a separate data path for the summer differential tap. In this way, the loading of an input stage of the summer circuit and the loading from the h1 unrolling loop are decoupled, allowing each split multiplexer to be configured according to a specific timing requirement along a respective data path. Thus, timing performance of the speculative decision feedback equalizer is improved.

System and method for decision feedback equalizers

A method for testing on-die capacitors is provided. The method comprises transmitting, during a first time period, a first modulated testing signal from a first transmitter port of a transmitter to a first receiver port of a receiver along a first path of a differential signal, the first receiver port connected to a first on-die capacitor in the receiver along the first path; driving, during the first time period, a constant voltage on a second transmitter port of the transmitter to a second receiver port of the receiver along a second path of the differential signal comprising a second on-die capacitor; and determining whether the first on-die capacitor is functional, based on the first modulated testing signal.

On-die receiver coupling capacitance testing

A circuit for receiving signals in an integrated circuit device. The circuit comprises a first equalizer circuit having a first input for receiving a first input signal and generating an output signal at a first output; a second equalizer circuit having a second input for receiving the output signal generated at the first output of the first equalizer circuit and having a second output; and a control circuit having a control output coupled to the second output of the second equalizer circuit; wherein the control circuit provides an offset cancellation signal or a loopback signal to the second output of the second equalizer circuit. A method of receiving signals in an integrated circuit is also described.

Circuit for and method of receiving signals in an integrated circuit device

A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.

Circuit for and method of receiving a signal in an integrated circuit device

An apparatus and method and system therefor relates generally to decision threshold control. In such an apparatus, an ac-coupler circuit is configured as a high-pass circuit path for a first frequency range. A buffer amplifier circuit is coupled in parallel with the ac-coupler circuit. The buffer amplifier circuit is configured as a low-pass circuit path for a second frequency range. An offset injection circuit is coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.

Low-power decision threshold control for high-speed signaling

In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.

Transmitter configured for test signal injection to test AC-coupled interconnect

An integrated circuit (IC) includes a serial-to-parallel converter configured to receive a serial input signal to provide one or more parallel output signals. The serial input signal is an M-level Pulse-Amplitude Modulated (PAM) signal, wherein M is a positive integer. The serial-to-parallel converter includes a data converter configured to receive the serial input signal and provide a data converter output signal. The data converter output signal represents information of the serial input signal with N1 bits, and N1 is a positive integer. An encoder is configured to encode the data converter output signal to provide encoder output signal with N2 bits, wherein N2 is a positive integer less than half of N1. One or more sub-deserializers are configured to receive the encoder output signal and generate the one or more parallel output signals.

Encoding scheme for processing pulse-amplitude modulated (PAM) signals

An integrated circuit and method for providing a differential transmission line driver are disclosed. One embodiment of the differential transmission line driver comprises a current mode logic (CML) stage, and a cross-coupled n-channel enhancement type metal-oxide semiconductor field-effect transistor (NMOS) stage, wherein the cross-coupled NMOS stage provides a feedback current to the CML stage, where each output voltage of the differential transmission line driver is characterized by symmetrical rising and falling edges.

Method and apparatus for providing a differential output driver with a cross-coupled cell

A driver circuit of an integrated circuit is described. The driver circuit comprises a signal node coupled to receive an output signal of the integrated circuit; an inductor circuit having a resistor coupled in series with an inductor between a first terminal and a second terminal, wherein the first terminal is coupled to the signal node; an electrostatic discharge protection circuit coupled to the second terminal of the inductor circuit; and an output node coupled to the second terminal of the inductor circuit. A method of generating an output signal is also disclosed.

Driver circuit and method of generating an output signal

At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.

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San Jose, CA, United States of America

Hsung Jai Im