Powerchip Semiconductor Manufacturing Corporation

Hsun-Kuei Chan

Chen-Chiu Hsue

Hung-Kwei Liao

Kai-An Hsueh

Li-Tsen Jiang

Ming-Te Huang

A memory structure including a substrate, a charge storage layer, a first gate, a first dielectric layer, and a second dielectric layer is provided. The substrate includes a memory cell region. The charge storage layer is located on the substrate in the memory cell region. The charge storage layer has a recess. The charge storage layer has a tip around the recess. The first gate is located on the charge storage layer. The first dielectric layer is located between the charge storage layer and the substrate. The second dielectric layer is located between the first gate and the charge storage layer.

Growing community of inventors

Hsinchu County, Taiwan

Hsun-Kuei Chan