Industrial Technology Research Institute

Hsun-Chih Liu

Rong Xuan

Yi-Keng Fu

Chen-Zi Liao

Yen-Hsiang Fang

Chih-Wei Hu

Hung-Lieh Hu

Chen-Peng Hsu

Yao-Jun Tsai

Chien-Jen Sun

Kuo-Feng Lin

Wei-Hung Kuo

Yih-Der Guo

Jenq-Dar Tsay

Tzung-Te Chen

Chu-Li Chao

Yu-Hsiang Chang

Chien-Ping Wang

Suh-Fang Lin

Ji-Feng Chen

Shang-Ping Ying

Chien-Pin Lu

Sheng-Huei Kuo

An apparatus for measuring of a curvature of a thin film, is adapted to measure the curvature of a thin-film. The apparatus includes a light emitting module, a first optical module, a second optical module, a third optical module, an image capture module, and an image analysis module. The light emitting module emits at least one line laser as an incident light whose cross-sectional shape is a geometric picture formed of lines. The incident light is transmitted through a first optical path formed of the first optical module, and is directed to incident the thin film by the second optical module. The reflected light is reflected by the thin film go through the second optical path, and is directed to transmit through the third optical path by the third optical module, and then is captured by the capture module to form a second geometric picture.

Thin-film curvature measurement apparatus and method thereof

A carrier for carrying a semiconductor layer having a growth surface and at least one nano-patterned structure on the growth surface is provided. The at least one nano-patterned structure on the growth surface of the carrier has a plurality of mesas, a recess is formed between two adjacent mesas, in which a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm.

Carrier for a semiconductor layer

A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.

Wafer-level light emitting diode structure, light emitting diode chip, and method for forming the same

A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer, in which the buffer layer includes n sub-buffer layers where n&#x2267;2, and each of the sub-buffer layers has island structures. The nitride semiconductor layer is disposed on the buffer layer.

Nitride semiconductor structure

A semiconductor structure including a silicon substrate, a nucleation layer and a plurality of multi-layer sets is provided. The nucleation layer is disposed on the silicon substrate. The multi-layer sets are stacked over the nucleation layer, and each of the multi-layer sets includes a plurality of first sub-layers and a plurality of second sub-layers stacked alternately. A material of the first sub-layers and the second sub-layers includes Al-containing III-V group compound, wherein an average content of aluminum of the multi-layer sets decreases as a minimum distance between each of the multi-layer sets and the silicon substrate increases, and an aluminum content of the first sub-layers is different from an aluminum content of the second sub-layers.

Semiconductor structure

A light emitting diode device may include a carrier, a p-type and n-type semiconductor layers, an active layer, a first electrode and a second electrode is provided. The carrier has a growth surface and at least one nano-patterned structure on the growth surface, in which the carrier includes a substrate and a semiconductor capping layer disposed between the substrate and the n-type semiconductor layer. The n-type semiconductor layer and the p-type semiconductor layer are located over the growth surface of the carrier. The active layer is located between the n-type and p-type semiconductor layers, in which a wavelength &#x3bb; of light emitted by the active layer is 222 nm&#x2266;&#x3bb;&#x2266;405 nm, and a defect density of the active layer is less than or equal to 5&#xd7;10/cm. The first and second electrodes are respectively connected to the n-type and p-type semiconductor layers. A carrier for carrying a semiconductor layer is also provided.

Light emitting diode

A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.

A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than 0. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency.

Light emitting diode chip, light emitting diode package structure, and method for forming the same

A nitride semiconductor template including a substrate, a mask layer, a first nitride semiconductor layer and a second nitride semiconductor is provided. The substrate has a plurality of trenches, each of the trenches has a bottom surface, a first inclined sidewall and a second inclined sidewall. The mask layer covers the second inclined sidewall and exposes the first inclined sidewall. The first nitride semiconductor layer is disposed over the substrate and the mask layer. The first nitride semiconductor layer fills the trenches and in contact with the first inclined sidewall. The first nitride semiconductor layer has voids located outside the trenches and parts of the mask layer are exposed by the voids. The first nitride semiconductor layer has a plurality of nano-rods. The second nitride semiconductor layer covers the nano-rods. The spaces between the nano-rods are not entirely filled by the second nitride semiconductor layer.

Nitride semiconductor template and fabricating method thereof

A method of manufacturing a light emitting diode element is provided. A first patterned semi-conductor layer, a patterned light emitting layer, and a second patterned semi-conductor layer are sequentially formed on an epitaxy substrate so as to form a plurality of epitaxy structures, wherein the first patterned semi-conductor layer has a thinner portion in a non-epitaxy area outside the epitaxy structures. A passivation layer covering the epitaxy structures and the thinner portion is formed. The passivation layer covering on the thinner portion is partially removed to form a patterned passivation layer. A patterned reflector is formed directly on each of the epitaxy structures. The epitaxy structures are bonded to a carrier substrate. A lift-off process is performed to separate the epitaxy structures from the epitaxy substrate. An electrode is formed on each of the epitaxy structures far from the patterned reflector.

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Taipei, Taiwan

Hsun-Chih Liu