Marvell International Limited

Hsui-Peng Peng

Jae-Hong Lee

A built-in self test (BIST) method and system for testing a memory included on an integrated circuit includes activating a component of the integrated circuit, partitioning the memory into a first part for use by non-BIST components and second part for BIST, and executing BIST on the second part of the memory while the component is operating. While the BIST is executing, the non-BIST components can access the first part of the memory and perform normal functional operations. The BIST method and system finds memory faults that are related to an I-R voltage drop due to the physical placement of the memory relative to power supply sources.

I-R voltage drop screening when executing a memory built-in self test

Described herein are methods and apparatuses for testing an integrated circuit chip including a thermal diode. According to various embodiments, a method for testing an integrated circuit chip including a thermal diode may comprise performing a test operation on the integrated circuit chip, and during the test operation, detecting a signal representative of a temperature sensed by a thermal diode embedded in the integrated circuit chip. Other embodiments may be described and claimed.

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San Jose, CA, United States of America

Hsui-Peng Peng