Industrial Technology Research Institute

Hsueh-Wu Kao

Yung-Yu Lin

Shu-Kuang Chou

A high-speed regeneration comparator is disclosed in the present invention. The high-speed comparator is consisted of two capacitors and two inverters. A first terminal of a first capacitor is coupled with a reference voltage through a first switch and with an inputting voltage through a second switch. The inputting terminal of a first inverter is coupled with a second terminal of the first capacitor and the inputting terminal of the first inverter is coupled with the outputting terminal of the first inverter through a third switch for feedback signals from the outputting terminal of the first inverter to the inputting terminal of the first inverter. A first terminal of a second capacitor is coupled with the outputting terminal of the first inverter. An inputting terminal of the second inverter is coupled with a second terminal of the second capacitor and the outputting terminal of the second inverter is coupled with the inputting terminal of the first inverter through a fourth switch and a fifth switch is coupled with the second inverter in parallel.

High speed regeneration comparator

A pseudo two-step current-mode analog-to-digital converter is disclosed, which carries out fine comparison in current mode such that the analog-to-digital conversion can be executed correctly even when the input signal is very small, and thus conserves chip area for implementing the series-connecting resistors. The analog-to-digital converter according to the present invention comprises: a reference voltage generator disposed between a first voltage (V1) and a second voltage (V2) to provide a plurality of reference voltage nodes; a first comparing device for comparing the analog input voltage with the reference voltages to output a set of rough codes; a first logic device selectively outputting corresponding bit codes as the output of the significant (higher) bits in accordance with the rough codes; a current conversion device for converting the analog input voltage and the voltage level corresponding to the significant bit codes to an analog input current and a significant-bit reference current respectively, and generating a plurality of fine reference currents; a second comparing device for comparing a differential current with the fine reference currents to output a set of fine codes, wherein the differential current is the difference between the analog input current and significant-bit reference current; a second logic device selectively outputting corresponding bit codes as the output of the least (lower) bits in accordance with the rough codes; and a output encoder receiving the significant bit codes and the least bit codes and outputting a set of digital codes after error correcting the significant bit codes.

Pseudo two-step current-mode analog-to-digital converter

A speed-enhancing comparator with cascaded inverters is disclosed. The comparator comprises: a first capacitor, a first inverter, and a first switch, wherein the first switch and the first inverter are connected in parallel, and a first terminal of the first capacitor is coupled to an input terminal of the first inverter; a first input switch and a second input switch, wherein input terminals of the first and second input switches are coupled to an input voltage and a reference voltage respectively, and both output terminals of the first and second input switches are coupled to a second terminal of the first capacitor; a second inverter, a second switch, and a third switch, wherein the second inverter and the third switch are connected in series and then connected in parallel with the second switch, and an output terminal of the first inverter is coupled to an input terminal of the second inverter; and a second capacitor, a third inverter, and a fourth switch, wherein the fourth switch and third inverter are connected in parallel, and a first terminal of the second capacitor is coupled to an input terminal of the third inverter, and a second terminal of the second capacitor is coupled to both output terminals of the second and third switches. The first to fourth switches and the first and second input switches carry out on/off operations, whereby the third inverter outputs a comparing result of the input voltage and the reference voltage.

Speed-enhancing comparator with cascaded inventors

The two-segment ladder circuit disclosed comprises a front-end resistor for reducing a reference voltage to an internal voltage, a resistor network for receiving the internal voltage and generating a plurality of branch currents having magnitude that form a decreasing geometrical series with a ratio of 1/2, and a resistor for terminating the resistor network. The terminating resistor and resistors of the resistor network can be diffused resistors or well resistors, which require less chip area. In addition, the front-end resistor can be a polysilicon resistor, which is capable of withstanding the high reference voltage and has less resistance variation according to the voltage across it. The two-segment ladder circuit can be used as a building block for a digital-to-analog converters.

Two-segment ladder circuit and digital-to-analog converter

Methods and circuits are disclosed which terminate charging of a battery when the maximum charge is reached. Maximum charge is reached when the battery voltage has peaked, after a long rise, and just starts to drop. This small voltage drop, or delta, is detected by a charger control which compares the real time battery voltage with a previously sampled battery voltage. Upon detecting this small voltage drop, the charger control terminates the charging process. Implementations using an analog delta voltage detection and a digital delta voltage detection are described.

Real time charging control of a fast battery charger

An analog to digital converter for the conversion of an analog input signal to a digital output code of n bits has a plurality of voltage references created in a voltage reference generator that divides the total range of voltage of the conversion input into increments of voltage equal to the smallest increment of resolution. The n bits of digital output are divided into most significant bits and least significant bits. The most significant bits are encoded from a set of digital signals that are formed in a set of coarse comparators, that compare the analog input signal with a subset of the voltage references representing the coarse range. The digital code that is the output of the coarse comparators is used to determine the selection of the subset of the plurality of the voltage references that are the fine voltage references. The least significant bits are encoded from a set of digital signals that are formed in a set of fine comparators that compare the analog input signal to the fine voltage references. The digital codes that form the most significant bits and the least significant bits are corrected encoded in an output encoder to form the digital output word.

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Hsinchu Hsien, Taiwan

Hsueh-Wu Kao