Advanced Semiconductor Engineering, Inc.

Hsueh-Te Wang

Meng-Jen Wang

Chien Cheng Liu

Chi-Hao Chiu

Su Tao

Chaur-Chin Yang

Jen-Kuang Fang

Wei-Chung Wang

Tai-Yuan Huang

A semiconductor package includes a flip chip mounted on a plurality of leads and encapsulated by a molding compound. The upper surfaces of the leads includes a plurality of bump-bonding regions at the fan-in ends of the leads, and the lower surfaces of the leads include a plurality of outer connecting regions at the fan-out ends of the leads. A plurality of indentations are formed at the upper surfaces of the leads and adjacent to the corresponding bump-bonding regions so as to avoid solder contamination on the leads. After molding, the indentations are filled with the molding compound. Preferably, the indentations have a reversed '&#x3a9;'-shaped profile to prevent bumps of the flip chip from excessively wetting over the other portions of the leads to firmly fix the fan-in ends of the leads.

Semiconductor package with a flip chip on a solder-resist leadframe

A quad flat flip chip package and a leadframe therefor are provided. A bump connection part is defined by bending or etching the leads of the leadframe. Thus, the bump formed after a reflow process is limited within the bump connection part, and the collapse of the bump can be prevented. Moreover, and the manufacturing costs of the package can be decreased and the process thereof can be simplified.

Quad flat flip chip package and leadframe thereof

A flip-chip type quad flat package and a leadframe. The leadframe comprises a bump-connecting area and a non-connecting area. The maximum width of the bump-connecting area is larger than the width of the non-connecting area. A bump is limited to the bump-connecting area after performing a reflow process so that the bumps are prevented from collapsing, the manufacturing cost is reduced and the process is simplified.

Flip-chip type quad flat package and leadframe

A stack type flip-chip package is described, including a substrate board, a first chip, a second chip, a packaging material and a heat sink. The substrate board has bump contacts and line contacts thereon, wherein the bump contacts connect with the bonding pads on the active surface of the first chip via bumps. The back surface of the first chip has a redistribution circuit thereon including bump pads and line pads exposed by a passivation layer, wherein the bump pads connect with the bonding pads of the second chip via bumps, and the line pads are connected to the line contacts via conductive wires. The packaging material encloses the first chip and the conductive wires, but may expose the back surface of the second chip, to which a heat sink can be directly bonded.

Stack type flip-chip package

A quad flat flip chip packaging process and a leadframe therefor are provided. A sacrificial film is attached on the leads of the leadframe for limiting the extent of bumps when formed and saving the manufacturing cost. Besides, the sacrificial film can be removed from the leadframe after a reflow step. Thus, the delamination between the molding compound material and the leads can be prevented during the molding step.

Quad flat flip chip packaging process and leadframe therefor

A stack type flip-chip package that utilizes a redistribution circuit on the back of a chip to serve as a bridge for connecting with other chips. The package includes at least a substrate, a first chip, a second chip, some underfill material and some packaging material. The substrate has a plurality of bump contacts and a plurality of line contacts thereon. The first chip has an active surface with a plurality of first bonding pads thereon. The back surface of the first chip has a redistribution circuit. The redistribution circuit has a plurality of bump pads and a plurality of line pads thereon. The second chip has an active surface with a plurality of second bonding pads thereon. Bumps are positioned between the bump contacts and the first bonding pads and between the bump pads and the second bonding pads. Conductive wires connect the line contacts and the line pads. The underfill material fills the space between the chip and the substrate and the gap between the first and the second chips. The packaging material encloses the chips and the conductive wires.

A method of making a stacked chip package comprises the steps of: (a) placing a first chip onto a substrate in a manner that solder bumps on the first chip are aligned with corresponding flip-chip pads formed on a surface of the substrate; (b) reflowing the solder bumps; (c) attaching a second chip to the first chip through an adhesive layer; (d) curing the adhesive layer; (e) forming an underfill between the first chip and the substrate; (f) curing the underfill; (g) electrically coupling the second chip to corresponding wire-bondable pads formed on the surface of the substrate; and (h) encapsulating the first chip and the second chip against a portion of the surface of the substrate. This invention is characterized in that the adhesive layer is cured before underfilling thereby forming a protection layer on the first chip. Therefore, the cured adhesive layer can help the first chip to resist stresses created during curing process of the underfill, thereby reducing the problem of die cracking.

Method of making stacked chip package

A flip-chip semiconductor device and a method for under filling the flip-chip semiconductor device are disclosed. The flip-chip semiconductor device is provided with a substrate and a die having a plurality of solder bumps for connecting to the substrate. Encapsulation material is under filled between the die and the substrate. The substrate has a non-mask area defied in a center portion thereof while the remaining surface area is covered by a solder mask. The non-mask area defines a hole in the center thereof so that the encapsulation material can be dispensed along all sides of the die to flow toward the non-mask area and stop when reaching the non-mask area whereby the encapsulation material does not block the hole and air between said die and the substrate is limited in a void formed around the hole and communicated with the atmosphere via the hole.

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Kaohsiung, Taiwan

Hsueh-Te Wang