Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsueh-Ju Chen

Chi On Chui

Kuo-Feng Yu

Jian-Hao Chen

Chih-Wei Lee

Wen-Hung Huang

Zoe Chen

Tsung-Da Lin

Yee-Chia Yeo

Huicheng Chang

Xiong-Fei Yu

Chi-On Chui

Te-Yang Lai

Cheng-Hao Hou

Pei Ying Lai

Cheng-Chieh Lin

A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.

Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same

Dipole engineering techniques are disclosed that incorporate dipole dopant and/or nitrogen into gate dielectrics (e.g., high-k dielectric layers thereof) to realize multi-threshold voltage transistor tuning of transistors. The dipole engineering techniques include (1) forming a dipole dopant source layer over gate dielectrics of some transistors, but not other transistors, (2) forming a mask over gate dielectrics of some transistors, but not other transistors, (3) performing a nitrogen-containing thermal drive-in process, and (4) removing the dipole dopant source layer and the mask after the nitrogen-containing thermal drive-in process. The nitrogen-containing thermal drive-in process diffuses nitrogen and dipole dopant (n-dipole dopant and/or p-dipole dopant) into unmasked gate dielectrics having the dipole dopant source layer formed thereon, nitrogen into unmasked gate dielectrics, and dipole dopant into masked gate dielectrics having the dipole dopant source layer formed thereon. Masked gate dielectrics without the dipole dopant source layer formed thereon remain undoped.

Incorporating nitrogen in dipole engineering for multi-threshold voltage applications in stacked device structures

A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.

Nanostructure field-effect transistor device and method of forming

Methods of fabricating semiconductor devices are provided. The method includes forming a first fin and a second fin over a substrate, and conformally forming a silicon oxide layer over the first fin using a first atomic layer deposition (ALD) process. The method also includes conformally forming a silicon nitride layer over the silicon oxide layer using a second ALD process, and forming an insulating layer to fill the trench between the first fin and the second fin over the substrate. The method further includes recessing the insulating layer, the silicon oxide layer, and the silicon nitride layer to form an isolation structure with a liner. In addition, the method includes forming a gate structure over the first fin, and forming a source region and a drain region in the first fin and on opposite sides of the gate structure.

Methods of fabricating semiconductor devices having isolation structures with liners

Growing community of inventors

Taipei, Taiwan

Hsueh-Ju Chen