Nan Ya Technology Corporation

Hsueh-Han Lu

Yu-Ting Lin

Chiang-Lin Shih

Tsang-Po Yang

Jui-Hsiu Jao

Yao Ching Chiu

Yu-Che Li

Ming Hsun Wu

A method of forming a semiconductor structure includes a number of operations. Conductors are formed in a first dielectric layer on a substrate. First conductive vias overlapping the conductors are formed in a second dielectric layer on the substrate. Electrodes are formed in a third dielectric layer on the substrate, wherein each of the electrodes overlaps one of the first conductive vias. A hard mask is formed on the third dielectric layer. Mandrel exposures are formed on the hard mask. Patterning spacers is formed on sidewalls of the mandrel exposures. The mandrel exposures are removed. The hard mask is patterned based on the patterning spacers and the third dielectric layer is patterned based on the patterning spacers to form conductive lines along the second direction in the third dielectric layer, wherein each of the conductive lines overlaps one of the first conductive vias.

Semiconductor structure and method of forming thereof

A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate and the bit line structure. A first landing pad is disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and electrically connects the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad, in which a first upper surface of the first landing pad is entirely covered by the conductive layer, and the conductive layer has a substantially planar upper surface.

Test structure for use in dynamic random access memory and manufacturing method thereof

A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Semiconductor structure and method of manufacturing the same

A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.

The semiconductor structure includes a substrate, a deep well, a first doped region, a source/drain region, and a first heavily doped region. The substrate has a first conductivity type. The deep well has a second conductivity type disposed on the substrate. The first doped region has the first conductivity type disposed on the deep well. The source/drain region has the second conductivity type disposed on the first doped region. The first heavily doped region has the second conductivity type disposed in a first top region of the source/drain region, in which the first conductivity type is opposite to the second conductivity type.

Semiconductor structure

A testing structure is disclosed. The testing structure includes a first layer, a second layer, and a third layer. The first layer includes a first pattern. The third layer includes a second pattern. The first layer, the second layer, and the third layer overlap each other. The second layer is connected to a CBCM (charged based capacitance measurement) testing circuit.

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Taipei, Taiwan

Hsueh-Han Lu