International Business Machines Corporation

United Microelectronics Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Globalfoundries Inc.

Industrial Technology Research Institute

Stmicroelectronics Gmbh

Other

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Globalfoundries U.S. Inc.

Elpis Technologies Inc.

Hsueh-Chung Chen

Yann Mignot

Chih-Chao Yang

Lawrence Alfred Clevenger

Yongan Xu

Hsien-Wei Chen

Su Chen Fan

Chanro Park

James John Kelly

Shin-Puu Jeng

Chi-Chun Liu

Yunpeng Yin

Chine-Gie Lou

Cornelius Brown Peethala

Ming-Sheng Yang

Shih-Hsun Hsu

Mary Claire Silvestre

Koichi Motoyama

Terry Allen Spooner

Juan-Yuan Wu

Junli Wang

Carl John Radens

Somnath Ghosh

Martin O'Toole

Hong He

Ravi Prakash Srivastava

Juntao Li

Teng-Chun Tsai

Chien-Hung Chen

Chia-Lin Hsu

Gwo-Shii Yang

Ailian Zhao

Chiung-Sheng Hsiung

Su-Chen Fan

Brendan O'Brien

Hao-Yi Tsai

Chun-chen Yeh

Water Lur

Fee Li Lie

Chiahsun Tseng

Tong-Yu Chen

Daniel James Dechene

Keith Donegan

Effendi Leobandung

Shang-Yun Hou

John H Zhang

Terence B Hook

Benjamin David Briggs

Injo Ok

Chih-Chien Liu

Hosadurga K Shobha

Nicholas Anthony Lanzillo

Muthumanickam Sankarapandian

Kafai Lai

Sean Teehan

Cheng Chi

Yiheng Xu

James J Demarest

Nicholas V Licausi

Jason Eugene Stephens

Richard Stephen Wise

Craig Child

Jed Walter Pitera

Shao-Chung Hu

Sung-Hsiung Wang

Art Yu

Lin Hu

Kangguo Cheng

Ruilong Xie

Theodorus E Standaert

Dechao Guo

Soon-Cheon Seo

Christopher J Penny

Ekmini Anuja De Silva

Hans-Joachim Barth

Erdem Kaltalioglu

Indira P Seshadri

Stuart A Sieg

Christopher Joseph Waskiewicz

Roger Allan Quon

Shahab Siddiqui

Raghuveer Reddy Patlolla

Jian-Hong Lin

Darryl D Restaino

Chien-Jung Wang

Yann A M Mignot

Louis DeWolf Lanzerotti

Yi-Lung Cheng

Dominik Metzler

Atsushi Ogino

Lai-Juh Chen

Linus Jang

Tzu-Kun Ku

Chingfu Lin

Kenneth Chun Kuen Cheng

Nikhil Jain

Jen Hui Chen

Jennifer A Oakley

Yung-Tsung Wei

Tsang-Jung Lin

A semiconductor device includes a conductive line disposed within a dielectric layer, a metal layer disposed over and in direct contact with the conductive line, and a metallization layer disposed over the metal layer such that a protruding segment of the metal layer acts as an interface between the conductive line and the metallization layer. The conductive line is copper (Cu) and the metal layer is ruthenium (Ru). The Ru metal layer includes an upper metal layer section and a lower metal layer section.

Dual-metal ultra thick metal (UTM) structure

A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

Metal lines with low via-to-via spacing

Disclosed is a memory device. The memory device comprises a cross-bar array of memory cells. The cross-bar array of memory cells comprises a plurality of bottom level lines arranged in a first direction. The cross-bar array of memory cells further comprises a plurality of vias arranged on top of each of the plurality of bottom level lines. The cross-bar array of memory cells further comprises a plurality of memory cells. Each memory cell is arranged on top of one of the plurality of vias. The cross-bar array of memory cells further comprises a plurality of top level lines arranged in a second direction that is substantially perpendicular to the first direction. Each top level line is arranged on top of and electrically connected to two or more memory cells.

Top via containing random-access memory cross-bar array

An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.

Electronic devices with a low dielectric constant

A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

MRAM top electrode structure with liner layer

Embodiments disclosed herein describe methods of forming semiconductor devices. The methods may include etching vias and trenches in a middle-of-line (MOL) layer that has a low-k dielectric layer, a sacrificial nitride layer, and a hard mask layer. The methods may also include depositing a thin nitride layer within the via trench, depositing a carbon layer on the thin nitride layer within the vias and trenches, etching back the thin nitride layer to expose a portion of the hard mask layer, removing the hard mask layer and the carbon layer, and removing the thin nitride layer and the sacrificial nitride layer.

Hard mask removal without damaging top epitaxial layer

A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.

Structure and method to pattern pitch lines

A top cap layer covering a first metal line and a second metal line, horizontally between the first metal line and the second metal line is, in sequential order, a post cap liner, an air gap and the post cap liner. A first set of metal lines embedded in an upper surface of a dielectric, a second set of metal lines embedded below the dielectric and above the electronic components, a post cap liner covering the first set of metal lines, a cavity which dissects a first metal line of the first set of metal lines and extends to a second metal line of the second set of metal lines and dissects the second set of metal lines. Forming a cavity in a first metal line embedded in an upper surface of a dielectric, where the first metal line and the dielectric are covered by a top cap layer.

Subtractive metal etch with improved isolation for BEOL interconnect and cross point

A redistribution layer for an integrated circuit package is provided. The redistribution layer includes a first conductive layer and a second layer disposed directly on the first conductive layer. The first conductive layer has a resistivity of less than 3.6*10Ω·m and has a thickness of greater than or equal to 1 μm. The second layer includes tungsten. An integrated circuit package is also provided that includes the redistribution layer electrically connecting a first integrated circuit of the first integrated circuit package to a first input/output of a frame of the integrated circuit package. The frame is connected to the first integrated circuit. A method for manufacturing a redistribution layer is also provided.

X-ray shielding structure for a chip

A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.

Dual color via patterning

Embodiments of the present invention are directed to fabrication methods and resulting structures having a back-end-of-line (BEOL) single damascene (SD) top via spacer defined by pillar mandrels. In a non-limiting embodiment of the invention, a first conductive line is formed in a first dielectric layer. A mandrel is formed over the first conductive line and a spacer is formed on a sidewall of the mandrel. A portion of a second dielectric layer is recessed to expose a top surface of the spacer and a top surface of the mandrel and the mandrel is removed. The spacer prevents damage to the second dielectric layer while removing the mandrel. The mandrel is replaced with a conductive material. A first portion of the conductive material defines a via and a second portion of the conductive material defines a second conductive line. The via couples the first conductive line to the second conductive line.

Back-end-of-line single damascene top via spacer defined by pillar mandrels

Provided is a semiconductor device and corresponding method of fabricating the same. The semiconductor device comprises a plurality of bottom lines. One or more top vias are arranged on top of the plurality of bottom lines. One or more electronic fuses (eFuses) are also arranged on top of the plurality of bottom lines. Each eFuse of the one or more eFuses is a via having a smaller critical dimension that the one or more top vias. A plurality of top lines are arranged on top of the one or more top vias and the one or more eFuses.

Electronic fuse structure embedded in top via

A semiconductor structure includes a plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines electrically communicates with a respective contact, a metal layer disposed over each of the plurality of conductive lines, a phase change memory (PCM) element disposed over the metal layer of each of the plurality of conductive lines, and a projection liner encapsulating the PCM element. Spacers directly contact sidewalls of the projection liner and the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

Wrap-around projection liner for AI device

Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.

Circuit design watermarking

A method of via formation including forming a sacrificial mask over a conductive layer, forming a plurality of pillars in the sacrificial mask and the conductive layer, wherein each pillar of the plurality of pillars includes a sacrificial cap and a first conductive via, depositing a spacer between the plurality of pillars, masking at least one of the sacrificial caps, removing at least one of the sacrificial caps to create openings, forming second conductive vias in the openings, and depositing a dielectric coplanar to a top surface of the second conductive vias.

Via CD controllable top via structure

Growing community of inventors

Cohoes, NY, United States of America

Hsueh-Chung Chen