United Microelectronics Corp.

Hsueh-Chen Cheng

Yu-Yee Liow

Po-Hua Chen

Wen-Hong Hsu

Ya-Nan Mou

Yuan-Hui Chen

Yung-Hsiang Lin

Cheng-Hsiao Lai

Ying-Ting Lin

Chai-Wei Fu

A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

Voltage regulating circuit

A phase-locked loop (PLL) and a method for controlling the PLL are provided. The PLL includes a phase detector, a charge pump, a voltage-controlled oscillator (VCO), a feedback frequency divider, and a detector circuit. The phase detector generates a direction signal according to a comparison between phases of a first clock signal and a second clock signal. The charge pump converts the direction signal into a control voltage. The VCO generates a third clock signal. The control voltage controls a frequency of the third clock signal. The feedback frequency divider divides the frequency of the third clock signal to generate the second clock signal. The detector circuit sends a pulse signal to restart the VCO when the control voltage conforms to a preset condition.

Phase-locked loop and method for controlling the same

A circuit and a method for restarting up a VCO of a PLL are introduced herein. The VCO restart up circuit receives a power down signal, an external signal, a clock output from the VCO and generates a trigger signal to the VCO to trigger the VCO clock to leave a stable mode. In other words, if the VCO clock is in the stable mode, the VCO restart up circuit generates one or more than one pulse on a trigger signal to restart up the VCO. Oppositely, if the VCO is not in the stable mode, there is no pulse on the trigger signal generated by the VCO restart up circuit and the VCO needs not to be restarted up.

VCO restart up circuit and method thereof

An asynchronous successive approximation register analog-to-digital converter includes a clock generator, a logic control unit, a sample and hold circuit, a digital-to-analog converter and a comparator. The clock generator is used to generate a clock signal. The logic control unit is for generating a sample and hold clock according to the clock signal. The sample and hold circuit is for sampling an analog signal according to the sample and hold clock to obtain and hold a sampling signal. The digital-to-analog converter is for generating a reference value according to a digital value transmitted from the logic control unit. The comparator is for generating a comparison value according to the sampling signal and the reference value.

Asynchronous successive approximation register analog-to-digital converter and operating method thereof

A DAC has at least one bit current-steering circuit. In the DAC, the current-steering circuit has a current source circuit, a switch, a feedback circuit, and an amplifier circuit. The current source circuit is disposed for outputting a bias current to the switch and coupled to the amplifier circuit. The switch has a first input/output terminal coupled to output an analog signal, a control terminal coupled to the feedback circuit, and a second input/output terminal for receiving the bias current, so that the first switch determines whether the first and the second input/output terminals are conducted according to a status of the control terminal.

Digital-to-analog converter with greater output resistance

A digital-to-analog converter includes a clock driver, a first decoder, a second decoder, a current source matrix, a pseudo random mode generator and at least one multiplexer. The first decoder and the second decoder are coupled to the clock driver. The current source matrix is coupled to the first decoder, and the pseudo random mode generator is used to randomly output a set of selecting signals. Each multiplexer of the at least one multiplexer includes a plurality of input ends coupled to a plurality of output ends of the second decoder, an output end coupled to the current source matrix, and a select end coupled to the pseudo random mode generator for controlling the output end to output a bit signal inputted from the input ends of the multiplexer according to one selecting signal of the set of selecting signals.

Growing community of inventors

Hsinchu County, Taiwan

Hsueh-Chen Cheng