Mediatek Corporation

Hsueh-Bing Yen

Chiung-Fu Chen

You-Ming Tsao

Po-Hua Huang

Techniques pertaining to dynamic enablement, disablement and adjustment of offset of a virtual periodic timing control signal based on one or more predefined events are described. A method may determine whether a first predefined event is beginning. The method may also enable an offset of the virtual periodic timing control signal for synchronizing one or more first system modules in response to a determination that the first predefined event is beginning. The one or more first system modules may be configured to control one or more operations of one or more second system modules. The one or more second system modules may be configured to process one or more image frames. The method may further determine whether the first predefined event is ending. The method may additionally disable the offset in response to a determination that the first predefined event is ending.

Dynamic enablement, disablement and adjustment of offset of a periodic timing control signal

A memory system has a memory device and a data migration control circuit. The memory device has a plurality of memory spaces accessed via a plurality of memory channels, respectively. The data migration control circuit controls a first stored data in a second memory space to migrate to a first memory space. When a first data piece of the first stored data is requested during data migration of the first data piece, the data migration control circuit blocks data access of the first data piece until the first data piece is fully stored into the first memory space, where a size of the first data piece is smaller than a size of the first stored data.

Method and apparatus for controlling data migration in multi-channel memory device

A method for performing dynamic configuration includes: freezing a bus between a portion of a dynamic configurable cache and at least one of a plurality of cores/processors by pending a request from the at least one of the cores/processors to the portion of the dynamic configurable cache during a bus freeze period, wherein the plurality of cores/processors are allowed to access the dynamic configurable cache and the at least one of the plurality of cores/processors is allowed to access the portion of the dynamic configurable cache; and adjusting a size of the portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for the at least one of the plurality of cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.

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Hsinchu, Taiwan

Hsueh-Bing Yen