Hitachi, Ltd.

Renesas Technology Corpoartion

Hsuan-Wen Wang

Atsushi Hasegawa

Lew Chua-Eoan

Shinichi Yoshioka

Rajesh Chopra

Jun-Wen Tsong

An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

Method and apparatus for controlling the flow of data between two circuits by generating one or more phase shifted clock signals

Interface circuit

Methods and an apparatus for buffering write operations are disclosed. In one embodiment, a processing system bursts data to a bus. The processing system includes a memory cache, a write buffer unit, and a control unit. The memory cache produces an address and data. Included in the write buffer unit are a plurality of data locations coupled to the memory cache. The control unit directs the first data to any of the plurality of data locations.

Write buffer with burst capability

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Sunnyvale, CA, United States of America

Hsuan-Wen Wang