Realtek Semiconductor Inc.

Hsuan-Ting Ho

Liang-Wei Huang

Ching-Yao Su

Sheng-Fu Chuang

Chia-Lin Chang

Yuan-Jih Chu

Kuei-Ying Lu

Shih-Hsiung Huang

Ming-Feng Hsu

Cheng-Han Lee

Chun-Hung Liu

Shih-Wei Wang

Chi-Shun Weng

Ta-Chin Tseng

Yun-Tse Chen

Kai-Yue Lin

Su-Liang Liao

Heng Cheong Lao

Po-Han Lin

Chih-Jung Chiang

Yang-Bang Li

The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

Digital-to-analog conversion apparatus and method having signal calibration mechanism

A method includes: generating a first signal according to a digital signal; filtering the first signal according to first filter coefficients of first filter to generate a second signal; adding a first reference signal with the second signal to generate a third signal; performing digital-to-analog conversion according to the first and third signals to generate and output an echo signal; performing analog-to-digital conversion according to the echo signal to generate a fourth signal; generating a fifth signal according to the digital signal and the fourth signal; and updating the first filter coefficients according to the fifth signal. Generating the fifth signal includes: generating second filter coefficients of second filter; updating the second filter coefficients according to a second reference signal and the fourth signal; obtaining a first and second representative coefficients of the second filter coefficients; and generating the fifth signal according to the first and second representative coefficients.

Analog echo cancelation method

A signal transceiver circuit, a method of operating a signal transmitting circuit, and a method of setting a delay circuit are provided. The signal transceiver circuit is used to send an output signal and receive an input signal, and includes: a delay circuit for delaying a first clock to generate a second clock; a first digital-to-analog converter (DAC) for converting a first digital signal into the output signal according to the first clock; a second DAC for converting the first digital signal into an echo cancellation signal according to the second clock; an analog front-end circuit for receiving the input signal and the echo cancellation signal and generating an analog signal; and an analog-to-digital converter (ADC) for converting the analog signal into a second digital signal.

Signal transceiver circuit, method of operating signal transmitting circuit, and method of setting delay circuit

An echo canceller system includes a data transmitter circuit and an echo canceller circuit. The data transmitter circuit is configured to receive a transmitted signal. The echo canceller circuit includes a first filter. The first filter is configured to generate a first filtered signal according to the transmitted signal and a filter coefficient vector. The filter coefficient vector is updated according to a high-frequency leakage process. The echo canceller circuit is further configured to generate an echo cancelling signal according to the first filtered signal. The data transmitter circuit is further configured to generate an output signal according to a received signal and the echo cancelling signal.

Echo canceller system and echo cancelling method

An echo cancelling system includes a data transmitter circuit and an echo canceller circuit. The data transmitter circuit is configured to receive a first transmitted signal. The first transmitted signal has a first sampling rate. The echo canceller circuit is configured to generate a second transmitted signal according to the first transmitted signal. The second transmitted signal has a second sampling rate. The second sampling rate is greater than the first sampling rate. The echo canceller circuit is further configured to generate an echo cancelling signal according to the second transmitted signal. The data transmitter circuit is further configured to generate an output signal according to a received signal and the echo cancelling signal.

Echo cancelling system and echo cancelling method

A method and a measuring apparatus for measuring noise of a device under test (DUT) is provided, wherein the DUT is connected to a link partner (LP) device via a cable, and the measuring apparatus is coupled to the DUT and LP device. The method includes: controlling the LP device to transmit a far-end data sequence to the DUT according to transmission data; controlling the DUT to recover the transmission data for generating aided-data sequence according to the transmission data, wherein the aided-data sequence is configured to perform cancellation with a received far-end data sequence to generate a cancellation result; generating a first noise value and a second noise value in a first training phase and a second training phase, respectively; and estimating noise from at least one circuit according to the first noise value and the second noise value.

Method and measuring apparatus for measuring noise of device under test

A transceiver circuit includes an ADC and an echo-cancellation circuit, wherein the echo-cancellation circuit includes a steady circuit, a transient circuit and an output circuit. In the operations of the transceiver circuit, the ADC is configured to perform an analog-to-digital conversion operation on an analog input signal to generate a digital input signal. The steady circuit is configured to generate a steady echo response according to a transmitting signal. The transient circuit is configured to generate an echo response adjustment signal according to a phase change of a clock signal used by the transmitting signal. The output circuit is configured to generate an output signal according to the digital input signal, the steady echo response, and the echo response adjustment signal.

Transceiver and signal processing method applied in transceiver

The present invention provides a receiver including an ADC, an echo-cancellation circuit and a control circuit. In the operations of the receiver, the ADC uses a clock signal to perform an analog-to-digital converting operation on an analog input signal to generate digital input signal, the echo-cancellation circuit refers to a plurality of tap coefficients to perform an echo-cancellation operation on the digital input signal to generate an output signal, and the control circuit is configured to control a phase of the clock signal inputted into the ADC. In addition, when the phase of the clock signal is adjusted, the control circuit calculates a plurality of updated tap coefficients according to the plurality of tap coefficients used by the echo-cancellation circuit in a previous time, for use of the echo-cancellation circuit.

Receiver and associated signal processing method

An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.

Analog to digital converter device and capacitor weight calibration method

This invention discloses a signal receiving device for Ethernet and a control method thereof. The signal receiving device includes a gain control circuit, an alien near-end crosstalk canceller, a noise canceller, and a DFE. The gain control circuit adjusts an input signal of the signal receiving device according to a setting parameter. The alien near-end crosstalk canceller cancels an alien near-end crosstalk interference. The noise canceller uses a first filter to cancel noises. The DFE uses a second filter to cancel an inter-symbol interference of the input signal. The method includes steps of: temporarily stopping the gain control circuit from updating the setting parameter before a seed collision occurs, and temporarily stopping one of the noise canceller and the decision feedback canceller from updating the first filter coefficient of the first filter or the second filter coefficient of the second filter temporarily during the seed collision.

Signal receiving device for Ethernet and control method thereof

A three-way handshaking method includes: controlling a first port in a first specific mode to send a first specific signal to a second port, and controlling the first port to enter a second specific mode; when the first port receives a second specific signal, determining the second port is in the second specific mode and controlling the first port to send a third specific signal to the second port; and when it is determined that the second port is in a third specific mode, controlling the first port to enter the third specific mode.

Three-way handshaking method and computer readable media

A united power module having an external input and a first input is provided. The united power module includes a load block, a protection circuitry and a detection block. The detection block includes an analog circuitry. The load block and an end of the protection circuitry are electrically coupled to the external input. The load block, the first input, and another end of the protection circuitry are electrically coupled to the detection block. The load block is supplied by an external power received from the external input. The protection circuitry receives the external power and outputs an auxiliary power. The analog circuitry receives a first power from the first input under a normal power supply state, or receives the auxiliary power under an auxiliary power supply state.

United power module and system using the same

A control method applied to an Operating-Mode Finite-State-Machine (OPFSM) arranged for deciding a behavior of a first port of an apparatus includes: controlling the OPFSM to enter a second local state from a first local state and controlling the first port to send a signal with a wakeup pattern to a link partner of the first port when the state of the OPFSM is the first local state, and a wakeup request bit is a first local value.

Control method applied to operating-mode finite-state-machine and computer readable media

A signal transmission method is provided. The method includes the following steps. First, an output signal filtered from a square wave signal by a high pass filter is received. Then, the output signal is sampled at each time interval, so as to generate the sampled values. Next, the sampled values are compared with at least one threshold to generate comparison results. Finally, a signal pattern corresponding to the output signal is identified according to the comparison results.

Signal transmission method and communication system using the same

This disclosure provides a network apparatus with communication ports, each connected to multiple channels, assigned a seed for eliminating the interference among the communication ports, and operable in a master or slave mode, each channel having a communication unit which comprises: an echo canceller, a near-end crosstalk (NEXT) canceller, a decision feedback equalizer, and a control unit configured for controlling the communication ports if the echo canceller and the decision feedback equalizer keep updating their filter coefficients according to the same symbol during a first pre-determined time-interval; wherein when more than two of the communication ports operate in the master mode, the control unit assigns different seeds to the more than two communication ports; and wherein when successive two of the communication ports operate in the slave mode, the control unit stops either the echo canceller or the NEXT canceller from updating their filter coefficients during a second pre-determined time-interval.

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Taichung, Taiwan

Hsuan-Ting Ho