Etron Technology, Inc.

Accton Technology Corporation

Eever Technology, Inc.

Hsuan-Ching Chao

Cheng-Pin Huang

Chih-Hung Huang

Yu-Chiun Lin

Kuo-Cyuan Kuo

Jie-Hau Huang

Hong-Chin Lin

Guu-Chang Yang

Huei-Chiang Shiu

Ming-Kia Chen

Chia-Chun Chiang

Cheng-Yuan Chang

Yung-Hsien Chang

An extensible host controller applied to a host includes a universal serial bus (USB) module, a control unit, and a peripheral component interconnect express (PCIE) bus. The USB module includes a USB unit and a predetermined unit. The PCIE bus is coupled to the control unit, wherein the PCIE bus supports a USB mode and a predetermined mode. When a first host with a first extensible host controller is connected to the USB module, the control unit makes the host utilize the USB mode and the USB unit, or the predetermined mode and the predetermined unit to communicate with the first host according to a determination way.

Extensible host controller of a host for optionally controlling the host to act as a target side or a host side and related operation method thereof

A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result.

Circuit for generating a clock data recovery phase locked indicator and method thereof

A circuit for simultaneously analyzing performance and bugs includes a mapping unit and a USB 3.0 data flow analyzer. The mapping unit is used for mapping commands transmitted to a USB 3.0 host through a peripheral component interconnect express and internal events of the USB 3.0 host to a packet of a USB 3.0 bus. The USB 3.0 data flow analyzer is used for analyzing performance and bugs of the USB 3.0 host through the packet of the USB 3.0 bus.

Circuit for simultaneously analyzing performance and bugs and method thereof

The present invention relates to both of a bi-stage correlation calculation demodulation system, and a fast walsh block demodulation device at a receiver, wherein the bi-stage correlation calculation demodulation system has a characteristic of bi-stage correlation calculation in which the subsequent second-stage correlation calculations are dependent on the first-stage correlation calculation results by utilizing an incomplete orthogonal property within CCK codewords to arrange the CCK codewords operated in the first-stage correlation calculations and second-stage correlation calculations properly and respectively. The fast walsh block demodulation device comprises: a plurality of adders (operators) constructed to be a first-level correlation calculation circuit and a second-level correlation calculation circuit, and a plurality of process modules constructed to be a third-level correlation calculation circuit, the process modules having the functions of picking one maximum value from four values and performing third-level correlation calculation of conventional basic fast walsh block demodulation device.

Complementary code keying demodulation system

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Keelung, Taiwan

Hsuan-Ching Chao