Vanguard International Semiconductor Corporation

Hsuan-Chi Su

Po-Yuan Tang

Yang-Sen Yeh

Jui-Lung Chen

Chia-Chiuan Chang

Yu-Chuan Chang

Ching-Hsiang Lin

Yu-Wen Chen

A level shifter receives an input signal through an input terminal and converts the input signal to an output signal. The level shifter includes an input stage circuit and an output stage circuit. The input stage circuit receives the input signal. The input stage circuit includes an N-type transistor that has a gate coupled to the input terminal, a drain coupled to a first node, a source coupled to a ground, and a bulk connected to the source. The output stage circuit is coupled to an output terminal and the first node. The output stage circuit includes a P-type transistor that has a gate, a source coupled to the supply terminal, a drain coupled to the first node, and a bulk disconnected from the source. The output signal is generated at the output terminal. An inverted output signal is generated at the first node.

Level shifter

A storage device including a cell array and a disturb-free circuit is provided. The cell array includes a first cell and a second cell. The first cell is coupled to a first conductive line and a specific conductive line. The second cell is coupled to a second conductive line and the specific conductive line. The disturb-free circuit performs a first write operation on the first cell and performs a verification operation on the second cell. The verification operation determines whether data stored in the second cell is disturbed by the first write operation. In response to the data stored in the second cell being disturbed by the first write operation, the disturb-free circuit performs a second write operation.

Storage device and control method thereof

An anti-fuse memory cell is provided. The anti-fuse memory cell includes a programmable transistor and a selection transistor. The programmable transistor includes a gate structure, a first doped region and a lightly doped region. The first doped region is divided into a first portion doped region, a second portion doped region and a third portion doped region. The first and second portion doped regions are respectively a source and a drain of the programmable transistor, and the third portion doped region is disposed between the first and second portion doped regions. The lightly doped region is distributed around a channel region of the programmable transistor, and adjacent to the first, second and third portion doped regions. The selection transistor includes a gate structure and a second doped region, and connected in series to the programmable transistor through the first portion doped region.

Anti-fuse one-time programmable memory cell and anti-fuse one-time programmable memory array

Growing community of inventors

Taoyuan, Taiwan

Hsuan-Chi Su