Hannstar Display Corporation

Hannstar Display (nanjing) Corporation

Hsuan-Chen Liu

Sung-Chun Lin

Chien-Ting Chan

Chia-Hua Yu

Hsien-Tang Hu

Chung-Lin Chang

Tean-Sen Jen

Yi-Chung Juan

Chang-Ching Yeh

Yu-Tuan Hsu

Kun-Chen Lee

Chen-Hao Su

Hsu-Ho Wu

Chia Hua Yu

Yu-Cheng Lin

Chien-Hao Wu

Chia-Te Liao

Da-Ching Tang

Te-Cheng Chung

Wei-Chi Lin

Wen-Chi Lin

Guang-Shiung Chao

Kun-Tsai Huang

Sweehan Jui-Hsien Yang

Po-Yi Chen

Ling-Chih Kao

Hsien-Cheng Chang

Chen-Yin Su

Ching-Chao Wang

Kun Cheng Lee

Yi-Tse Lin

Jung-Chen Lin

Huang-Chen Kao

A display device has a display area and a peripheral area, and includes an array substrate. The array substrate includes M number of pixel unit columns disposed in the display area and a first dummy electrode disposed in the peripheral area, where M is a positive integer greater than or equal to 2. The M number of pixel unit columns include a first pixel unit column to an Mpixel unit column arranged in sequence. Each of the M number of pixel unit columns includes a plurality of pixel units arranged in sequence. The first dummy electrode is located on one side of the first pixel unit column. During a frame period, the first pixel unit column receives the first pixel signal, and the first dummy electrode receives the first dummy signal. The polarity of the first pixel signal is different from that of the first dummy signal.

Display device

A privacy device and a privacy display apparatus are provided. The privacy device includes a first substrate, a first privacy electrode, first to fourth pads, a connection electrode, a second substrate, a liquid-crystal layer, a second privacy electrode, and a sealant. The first privacy electrode and the connection electrode are disposed on the first substrate. The first and second pads are coupled to the first privacy electrode. The third and fourth pads are coupled to the connection electrode. The first and second pads are disposed between the third pad and the fourth pad. The liquid-crystal layer and the sealant are disposed between the first substrate and the second substrate. The sealant includes multiple conductors. The connection electrode, the sealant, and the second privacy electrode are in a non-display area and overlap with each other along a direction perpendicular to a top surface of the first substrate.

Privacy device and privacy display apparatus

A display panel has an odd-shaped active area and a peripheral area. The display panel includes a substrate, pixel units, gate lines and at least one dummy thin film transistor. The pixel units are disposed on the active area of the substrate. The gate lines are disposed on the substrate, each of the gate lines is coupled to one or more of the pixel units, and the number of pixel units coupled to a first gate line of the gate lines is smaller than the number of pixel units a second gate line coupled to of the gate lines. The dummy thin film transistor is disposed on the substrate, and is coupled to the first gate line.

Notched display panel

The present invention provides a display panel having a display region and a peripheral region, and the display panel includes a plurality of pixel units including at least one inner pixel unit and at least one first peripheral pixel unit, and a shielding layer. A shape of the display region is non-rectangular. The inner pixel unit is disposed in the display region and includes at least one inner sub-pixel unit. The first peripheral pixel unit is disposed in both the display region and the peripheral region and includes at least one first peripheral sub-pixel unit. At least a part of the shielding layer is disposed in the peripheral region, and the at least a part partially overlaps the first peripheral pixel unit. A structure of the first peripheral pixel unit is different from a structure of the inner pixel unit.

Display panel

A gate driving circuit and a display panel with the gate driving circuit are provided. The gate driving circuit includes shift registers for providing scan signals to gate lines of the display panel. Each shift register includes a main circuit and a discharge circuit. In the main circuit, a pre-charge unit is coupled to a first node and is configured to output a pre-charge signal to the first node, a pull-up unit is coupled to the first node and a second node and is configured to output an mstage scan signal of the 1to Nstage scan signals to the second node; and a reset unit is coupled to the first node and is configured to receive a reset signal. In the discharge circuit, a pull-down unit is coupled to the first node and the second node and is configured to receive a pull-down control signal.

Gate driving circuit and display panel

A display panel includes a substrate having a display region and a peripheral region, first and second sub pixels, first and second gate driving units. The display region includes a first area having first scan lines and first sub pixels and a second area having second scan lines and second sub pixels. A portion of the first sub pixels and a portion of the second sub pixels are respectively electrically connected to the first and second scan line. The first gate driving unit includes a first driving transistor. The second gate driving unit includes a second driving transistor. The number of the first sub pixels driven by the first gate driving unit is less than the number of the second sub pixels driven by the second gate driving unit. The channel width of the first driving transistor is less than the channel width of the second driving transistor.

Display panel and method of improving display quality in peripheral regions thereof

A display panel including a first substrate, a second substrate opposite to the first substrate, and a display medium located between the first substrate and the second substrate is provided. The display panel further includes a plurality of pixel structures, a plurality of data lines and a plurality of scan lines electrically connected to the pixel structures, a first driving unit located at a peripheral area, at least one test line, and at least one first pad located at the peripheral area. Each of the data lines has a first end and a second end opposite to each other. The first driving unit is electrically connected to the first ends of the data lines. The at least one test line is electrically connected to the second ends of at least part of the data lines. The at least one test line is grounded through the at least one first pad.

Display panel having a test line therein

A thin film transistor substrate having a display region and a peripheral region, and the thin film transistor substrate includes a first substrate, scan lines, data lines, an insulating layer, first thin film transistors, at least one passivation layer and at least one gate driving circuit. The first substrate has an electrostatic protection area and a driving circuit area, and the electrostatic protection area and the driving circuit area are situated in the peripheral region. The scan lines, the data lines and the first thin film transistors are disposed in the display region. The insulating layer includes a gate insulator of the first thin film transistor, and the passivation layer is disposed on the insulating layer. The gate driving circuit is disposed in the driving circuit area. At least one of the passivation layer and the insulating layer are not disposed in the electrostatic protection area.

Thin film transistor substrate and display device

In a shift register, a pre-charge unit is configured to receive a first input signal and output a pre-charge signal to a first node, a pull-up unit is configured to output a scan signal to a second node, and a pull-down unit is configured to receive a pull-down control signal. The pull-down control signal switches from a disable voltage to an enable voltage before the display panel switches from a non-display status to a display status.

Gate driving circuit and display panel with reset function

An electronic product includes a substrate and a bonding pad structure. The bonding pad structure is disposed on the substrate, and the bonding pad structure includes a first metal layer, a first insulating layer, at least one first connecting hole and a transparent conductive layer. The first metal layer and the first insulating layer are disposed on the substrate. The first connecting hole is situated in the first insulating layer, and the first connecting hole exposes a portion of the first metal layer. The transparent conductive layer is disposed on the first insulating layer, and the transparent conductive layer has a first edge and a second edge opposite to the first edge, wherein the transparent conductive layer is electrically connected to the first metal layer through the first connecting hole. A spacing between the first edge and the first connecting hole is greater than or equal to 100 &#x3bc;m.

Electronic product

An electronic device includes a first substrate, a second substrate, a plurality of first metal line segments and a shielding layer. The second substrate is opposite to the first substrate. The first metal line segments are disposed on the first substrate and extend along a first direction, wherein at least one of the first metal line segments includes a first alignment part and a first trace part, a width of the first alignment part is larger than a width of the first trace part, and the first alignment parts are arranged along a second direction. The shielding layer is disposed on the second substrate, and the shielding layer includes a plurality of first alignment structures, wherein one of the first alignment parts is aligned with one of the first alignment structures in a normal vector of the first substrate.

Electronic device

A liquid crystal display device includes a plurality of pixel units, an electrode line surrounding the pixel units, at least one gate driver coupled with the pixel units via a plurality of gate lines, and at least one electrostatic discharge protection circuit coupled with the at least one gate driver and the electrode line.

Liquid crystal display

A pixel structure includes a first substrate, a thin-film transistor, a second insulation layer, a first transparent conduction layer and a second substrate. The thin-film transistor includes a gate electrode formed on the first substrate, a semiconductor layer formed on the gate electrode, a first insulation layer located between the semiconductor layer and the gate electrode, and an electrode layer including a source electrode and a drain electrode. The source electrode covers a portion of the semiconductor layer. The drain electrode covers a portion of the semiconductor layer. The second insulation layer covers the thin-film transistor. The first transparent conduction layer is formed on the second insulation layer. An opening is formed in the first transparent conduction layer along a fringe of the semiconductor layer.

Pixel structure

The present invention provides a driving circuit and a display device. The driving circuit is disposed on a substrate of the display device. The driving circuit includes thin film transistors (TFTs), a capacitor and clock signal lines. Each of the TFTs includes a gate, a source and a drain. The capacitor is coupled to at least one of the TFTs, and includes a first and a second electrode. The material of the first and the second electrode includes a transparent conductive material. The clock signal lines extend along a first direction. The source and the drain of at least two of the TFTs respectively extend along a second direction. The angle between the first direction and the second direction is between 80 degrees and 100 degrees. At least a partial structure of the capacitor is located in a gap between adjacent ones of the TFTs.

Driving circuit and display device with enhanced moisture prevention capability

In a display panel, multiple first alignment patterns are disposed in a non-display area on a first substrate, and each first alignment pattern includes a first portion and a second portion connected to each other. Multiple second alignment patterns are disposed in the non-display area on a second substrate, and each of the second alignment patterns includes a third portion and a fourth portion. There is a first length difference between the length of each first portion along a first direction and the length of the corresponding third portion along the first direction, and the first length differences are different from each other. There is a second length difference between the length of each second portion along a second direction and the length of the corresponding fourth portion along the second direction, and the second length differences are different from each other.

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Kaohsiung, Taiwan

Hsuan-Chen Liu