United Microelectronics Corp.

Hsu Ting

Yu-Ren Wang

Chun-Wei Yu

Kuang-Hsiu Chen

Chueh-Yang Liu

Yu-Ying Lin

Yi-Liang Ye

Keng-Jen Lin

Bin-Siang Tsai

Da-Jun Lin

Neng-Hui Yang

Chung-Fu Chang

Po-Jen Chuang

Ting-An Chien

Chia-Ming Kuo

Yen-Hsing Chen

Fu-Jung Chuang

Chun-Jen Chen

Shih-Wei Su

Ted Ming-Lang Guo

Shi-You Liu

Hao-Hsuan Chang

Chih-Wei Chang

Yao-Hsien Chung

Sung-Yuan Tsai

A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.

Fabricating method of reducing photoresist footing

A semiconductor device comprises at least one gate structure disposed on a substrate; a first dielectric layer disposed on the substrate and contacting an outer sidewall of the at least one gate structure; a second dielectric layer having a L shape disposed on the first dielectric layer and contacting the outer sidewall of the at least one gate structure; an etch stop layer contacting the second dielectric layer, the first dielectric layer and the substrate, wherein the second dielectric layer has an upper portion and a lower portion contacting the upper portion, the upper portion extends along the outer sidewall, the lower portion extends from the outer sidewall to the etch stop layer; and an air gap between the second dielectric layer and the etch stop layer; wherein the first dielectric layer and the lower portion of the second dielectric layer have a same width.

Semiconductor device and method for manufacturing the same

A semiconductor device includes: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, in which the epitaxial layer includes a planar surface and protrusions adjacent to two sides of the planar surface. Preferably, a contact plug is embedded in part of the epitaxial layer, and a silicide is disposed under the contact plug, in which a bottom surface of the silicide includes an arc.

Semiconductor device having epitaxial layer with planar surface and protrusions

A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.

Method for processing semiconductor device

A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.

Semiconductor device and manufacturing method thereof

A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

Method for fabricating semiconductor device with strained silicon structure

A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.

Method of forming semiconductor device having wick structure

An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

Apparatus for semiconductor wafer treatment and semiconductor wafer treatment

The invention provides a fabricating method of a FinFET, comprising: providing a substrate having fin structures; depositing an dielectric layer on the substrate filling between the fin structures; forming recesses to reveal a portion of the fin structure by removing a portion of the dielectric layer; performing a cleaning process on using a cleaning solution selected from one of a first solution, consisting of dHF and HO, and a second solution, consisting of dHF and DIO; forming a gate structure across on the fin structures; and forming a source/drain structure on the substrate at two lateral sides of the gate structure. The present invention also provides a fabricating method of a FinFET having an improved cleaning step using a cleaning solution having one of a third solution, consisting of dHF and DIO, and a fourth solution, consisting of NHOH and DIObefore formation of the source/drain structure.

Fabricating method of fin field effect transistor (FinFET)

Semiconductor device having the insulating layers cover a bottom portion of the fin shaped structure

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate and a first spacer adjacent to the first gate structure; forming a first epitaxial layer in the substrate adjacent to the first gate structure; forming a first hard mask layer on the first gate structure; removing part of the first hard mask layer to form a protective layer on the first epitaxial layer; and removing the remaining first hard mask layer.

Method of removing a hard mask layer on a gate structure while forming a protective layer on the surface of a substrate

A method for manufacturing semiconductor devices includes following steps. A substrate including a first gate structure and a second gate structure formed thereon is provided. The first gate structure and the second gate structure are complementary to each other. Next, a first mask layer covering the second gate structure is formed and followed by forming first recesses in the substrate at two respective sides of the first transistor. Then, forming the first recesses, a first epitaxial layer is formed in each first recess. After forming the first epitaxial layers, a local protecting cap is formed on the first epitaxial layers and followed by removing the first mask layer.

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Tainan, Taiwan

Hsu Ting