Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsiu-Ying Cho

Chin-Wei Kuo

Min-Chie Jeng

Wen-Sheh Huang

Jiun-Kai Huang

Transmission line structures are provided. The first and second conductive lines are formed in a metal layer over the semiconductor substrate and extend in a first direction. The first transmission line includes a first sub-line extending in the first direction, a plurality of second sub-lines extending toward the first conductive line, and a plurality of third sub-lines extending toward the second conductive line. The first dielectric material zones are formed between the second sub-lines and the first conductive line. The second dielectric material zones are formed between the third sub-lines and the second conductive line. The first and second dielectric material zones are separated from the first and second conductive lines and the first transmission line by an insulation material. Dielectric constant of the insulation material is less than that of the first and second dielectric material zones.

Transmission line structure with protruding sub-lines and dielectric zones for RF signal

A device includes a transmission line structure including a signal line, a shielding structure conductive strips spaced apart from one and another and having lengthwise directions substantially perpendicular to a lengthwise direction of the signal line, a first transistor electrically coupled to the transmission line structure, and a second transistor electrically coupled to at least one of the conductive strips to control the at least one of the conductive strips to be electrically coupled to ground or electrically floating.

Semiconductor device and manufacturing method thereof

An exemplary device includes a dielectric layer and a transmission line structure disposed in the dielectric layer. The transmission line structure includes a first metal line disposed between a second metal line and a third metal line. Dielectric islands are disposed in a first region and a second region of the dielectric layer. The first region of the dielectric layer is between the first metal line and the second metal line. The second region of the dielectric layer is between the first metal line and the third metal line. A dielectric constant of the dielectric islands is greater than a dielectric constant of the dielectric layer. The dielectric islands may be doped sections of the dielectric layer. In some embodiments, the dielectric islands in the first region are aligned with the dielectric islands in the second region along a direction perpendicular to a lengthwise direction of the first metal line.

Transmission line structures for three-dimensional integrated circuit and the methods thereof

De-embedding apparatus and methods of de-embedding are disclosed. A de-embedding apparatus includes a test structure including a device-under-test (DUT) embedded in the test structure, and a plurality of dummy test structures including an open dummy structure, a distributed open dummy structure, and a short dummy structure. The distributed open dummy structure may include a first signal transmission line coupled to a left signal test pad and a second signal transmission line coupled to a right signal test pad, the first and second signal transmission lines having a smaller total length than a total length of signal transmission lines of the open dummy structure, and intrinsic transmission characteristics of the DUT can be derived from transmission parameters of the dummy test structures and the test structure.

Method for de-embedding a device-under-test

A vertical inductor structure in a semiconductor device includes a plurality of vertically oriented spirals that produce magnetic field in a dielectric material above the surface of a semiconductor substrate thereby preventing any eddy currents from propagating in the substrate. An inductor shield structure is also provided. The inductor shield structure is formed over the substrate surface and between an inductor such as the vertical inductor structure or other inductor types and also prevents eddy currents from being induced in the substrate. The inductor shield may surround the inductor to various degrees.

Vertical slow-wave symmetric inductor structure for semiconductor devices

An integrated circuit includes a substrate having a surface and an inductor disposed over the surface of the substrate. The inductor includes a first conductive line disposed over the surface and first conductive structures disposed over and electrically coupled with the first conductive line. The inductor includes second conductive structures disposed over and electrically coupled with the first conductive structures. The inductor includes a second conductive line disposed over and electrically coupled with the second conductive structures. The inductor includes third conductive structures disposed over and electrically coupled with the first conductive line and at least one fourth conductive structure disposed over and electrically coupled with the third conductive structures. The inductor includes a third conductive line disposed over and electrically coupled with the at least one fourth conductive structure, the third conductive line extending substantially parallel to the second conductive line.

Integrated circuits including inductors

The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature.

Vertically oriented semiconductor device and shielding structure thereof

The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a horizontal surface. The method includes forming an interconnect structure over the horizontal surface of the substrate. The forming the interconnect structure includes forming an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The forming the interconnect structure includes forming a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members.

Method of fabricating a vertically oriented inductor within interconnect structures and capacitor structure thereof

A planar interdigitated capacitor structure, methods of forming, and devices including, the same. The device includes first and second planar electrode structures including respective first and second pluralities of planar continuous rectangular plate electrode elements formed above a semiconductor substrate and extending continuously in first and second orthogonal directions substantially parallel to a plane of the substrate, and first and second conductors interconnecting the respective first and second pluralities of planar electrode elements parallel to a third axis substantially normal to the plane of the substrate. The first and second planar electrode structures are arranged with respective continuous rectangular plate electrode elements of each planar electrode structure interleaved and substantially parallel with each other between the first and second conductors. The device also includes a dielectric material between the first planar electrode structure and the second planar electrode structure.

Planar interdigitated capacitor structures and methods of forming the same

A method includes simulating characteristics of a first transmission line having a first length, and simulating characteristics of a second transmission line having a second length greater than the first length. A calculation is then performed on the characteristics of the first transmission line and the characteristics of the second transmission line to generate intrinsic characteristics of a third transmission line having a length equal to a difference of the second length and the first length.

Transmission line characterization using EM calibration

The present disclosure relates to a semiconductor device, such as a transistor. The device includes a gate terminal, a source terminal, a drain terminal, a transconductance component, and a boost component. The gate terminal is configured to receive a bias voltage. The drain terminal is coupled to the boost component. The transconductance component is coupled to the gate terminal, the source terminal and the drain terminal and provides an output current proportional to the bias voltage. The boost component is coupled to the transconductance component and boosts the output current at a selected frequency range.

MOS transconductance gain boosting techniques in millimeter-wave range

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate that spans in an X-direction and a Y-direction that is orthogonal to the X-direction. The semiconductor device includes an interconnect structure formed over the substrate in a Z-direction that is orthogonal to both the X-direction and the Y-direction. The interconnect structure includes a plurality of metal lines interconnected together in the Z-direction by a plurality of vias. The interconnect structure contains a capacitor that includes an anode component and a cathode component. The anode component includes an array of elongate anode stack elements extending in the Z-direction. The cathode component includes an array of elongate cathode stack elements extending in the Z-direction. The array of anode stack elements are interdigitated with the array of cathode stack elements in both the X direction and the Y direction.

Vertical interdigitated semiconductor capacitor

The present disclosure involves a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an electronic device positioned over the substrate. The electronic device includes an opening. The semiconductor device includes a shielding device positioned over the substrate and surrounding the electronic device. The shielding device includes a plurality of elongate members. A subset of the plurality of elongate members extend through the opening of the electronic device. At least one of the electronic device and the shielding device is formed in an interconnect structure positioned over the substrate.

The present disclosure involves a semiconductor device. The semiconductor device includes a substrate having a horizontal surface. The semiconductor device includes an interconnect structure formed over the horizontal surface of the substrate. The interconnect structure includes an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The interconnect structure includes a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members.

Growing community of inventors

Hsinchu, Taiwan

Hsiu-Ying Cho