Episil Technologies Inc.

Hsiu-Wen Hsu

A semiconductor device comprising the following. A structure having: a capacitor; a first resistor; and a second resistor each within at least a portion of an oxide structure and a metal-oxide semiconductor electrode not within at least a portion of the oxide structure. The capacitor comprising: a lower capacitor first doped polysilicon portion; a capacitor interpoly oxide film portion thereover; and an upper capacitor second doped polysilicon portion over at least a portion of the capacitor interpoly oxide film portion. The first resistor comprising a lower first resistor first doped polysilicon portion and an upper first resistor second doped polysilicon portion thereover. The second resistor comprising a lower second resistor first doped polysilicon portion and an upper interpoly oxide film portion thereover. The metal-oxide semiconductor electrode comprising a lower metal-oxide semiconductor first doped polysilicon portion and an upper metal-oxide semiconductor second doped polysilicon portion thereover.

Method of forming a semiconductor device having a capacitor and a resistor

A method of simultaneously forming at least: one capacitor two resistors and one metal-oxide semiconductor. A first doped polysilicon layer/patterned interpoly oxide film/second doped polysilicon layer is formed over an exposed oxide structure. The patterned interpoly oxide forms a capacitor interpoly portion within a capacitor region and a second interpoly portion within a second resistor region. A second doped polysilicon layer is formed over the structure. The doped first and second polysilicon layers are patterned to form: a lower capacitor doped first polysilicon portion and an overlying upper capacitor second doped polysilicon portion; a lower first resistor first polysilicon portion and an upper, overlying first resistor second polysilicon portion; a lower second resistor first polysilicon portion; and a lower metal-oxide semiconductor first polysilicon portion and an overlying metal-oxide semiconductor second polysilicon portion.

A method for fabricating a power MOSFET, comprising an epitaxial layer, a gate dielectric layer and a gate layer formed on a substrate, the gate dielectric layer and the gate layer defined to form a gate structure, a stacked mask and the surface of the epitaxial layer partially exposed between the gate structure and the stacked mask, a well region formed in the epitaxial layer and partially under the gate structure and the stacked mask, a source region is formed in the well region between the gate structure and the stacked mask, a patterned dielectric layer exposing the top of the stacked mask formed over the substrate, the stacked mask removed to form a contact opening exposing the surface of the well region partially and a body region formed in the well region under the contact opening.

Method for fabricating power mosfet

A method for fabricating a trench power MOSFET, comprising an epitaxial layer and a mask layer formed over a substrate, a trench formed in the epitaxial layer and the mask layer, a gate oxide layer formed on the trench, then the mask layer removed, a body well region formed in the epitaxial layer beside the trench, a source region formed in and adjacent to the body well region, and a spacer formed on the sidewalls of the exposed gate layer exposing the source region partially. Masking by spacer, an opening exposing the body well is formed by partially removing the source region and the gate layer. A body region is formed in the body well region under the opening. A silicide layer is formed on the surfaces of the gate layer and the opening.

Method for fabricating a trench power MOSFET

A method for fabricating trench power MOSFET is described. An epitaxial layer and a mask layer having a first opening are sequentially formed on a substrate. A pair of spacers is formed on the sidewalls of the first opening. A second opening exposing the surface of the epitaxial layer is formed by removing a portion of the mask layer. The spacers are removed and then a trench is formed in the epitaxial layer using the mask layer as a mask. The mask layer is removed and a gate oxide layer is formed over the epitaxial layer and the surface of the trench. A gate layer is formed to fill the trench. A body well region is formed in the epitaxial layer adjacent to the sidewalls of the trench. A source region is formed in the body well region on each side at the top of the trench.

Method for fabricating trench power MOSFET

The present invention relates generally to semiconductor fabrication and more specifically to simultaneous formation of capacitors, resistors and metal oxide semiconductor.

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Hsinchu, Taiwan

Hsiu-Wen Hsu