Super Group Semiconductor Co., Ltd.

Niko Semiconductor Co., Ltd.

Great Power Semiconductor Corp.

Hsiu-Wen Hsu

Chun-Ying Yeh

Chih-Cheng Hsieh

Yuan-Ming Lee

Sung-Nien Tang

Ho-Tai Chen

Chun-Wei Ni

Yuan-Shun Chang

Kao-Way Tu

Chung-Ming Leng

Yi-Yun Tsai

Kou-Way Tu

Chun Wei Ni

A power device and a method for manufacturing the power device are provided. The power device includes an electrical substrate, an epitaxial compound layer, a plurality of gates, a passivation layer, an electrically conductive body, a drain, and a field plate. The electrical substrate has a first surface, an epitaxial drift layer, and a plurality of doping regions. The doping regions are located below the first surface. The epitaxial compound layer is located on the electrical substrate. The gates are located on the epitaxial compound layer. The passivation layer covers the gates and the epitaxial compound layer. The electrically conductive body penetrates the passivation layer and the epitaxial compound layer and extends to the first surface. The drain penetrates the passivation layer and extends to the epitaxial layer. The field plate is located on the passivation layer, shields the gates, and connects to the electrically conductive body.

Power device and method for manufacturing the same

A trench power semiconductor component and a method of manufacturing the same are provided. In the method, a step of forming a trench gate structure includes the following steps. First, a shielding electrode, a bottom insulating layer, and an upper insulating layer are formed in a trench. The bottom insulating layer covers a lower part of an inner wall of the trench, and surrounds the shielding electrode. The upper insulating layer covers an upper part of the inner wall. Thereafter, an interlayer dielectric layer and a U-shaped masking layer are formed in the trench. The interlayer dielectric layer is interposed between the upper insulating layer and the U-shaped masking layer. A portion of the upper insulating layer and a portion of the interlayer dielectric layer which are located at an upper part of the trench are removed so as to form an inter-electrode dielectric layer.

Trench power semiconductor component and method of manufacturing the same

A semiconductor power device and a manufacturing method thereof are provided. In the manufacturing method, before the self-aligned silicide process is performed, a gate stacked structure and a spacer are formed on a semiconductor layer having a body region and a source region. The spacer defines a portion of the source region for forming a silicide layer. Subsequently, the self-aligned silicide process is performed with the gate stacked structure and the spacer functioning as a mask to form the silicide layer at the defined portion of the source region. Thereafter, an interconnection structure including an interlayer dielectric layer and a source conductive layer is formed on the semiconductor layer. The source conductive layer is electrically connected to the source region. The silicide layer extends toward the gate stacked structure from a position under the source conductive layer to another position under the interlayer dielectric layer.

Semiconductor power device and manufacturing method thereof

A trench power semiconductor device and a manufacturing method thereof are provided. The trench power semiconductor device includes a substrate, an epitaxial layer disposed on the substrate, and a gate structure. The epitaxial layer has at least one trench formed therein, and the gate structure is disposed in the trench. A gate structure includes a lower doped region and an upper doped region disposed above the lower doped region to form a PN junction. The concentration of the impurity decreases along a direction from a peripheral portion of the upper doped region toward a central portion of the upper doped region.

Trench power seminconductor device and manufacturing method thereof

The present disclosure provides a trench power semiconductor component and a method of making the same. The trench power semiconductor component includes a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is disposed on the substrate, the epitaxial layer having at least one trench formed therein. The trench gate structure is located in the at least one trench. The trench gate structure includes a bottom insulating layer covering a lower inner wall of the at least one trench, a shielding electrode located in the lower half part of the at least one trench, a gate electrode disposed on the shielding electrode, an inter-electrode dielectric layer disposed between the gate electrode and the shielding electrode, an upper insulating layer covering an upper inner wall of the at least one trench, and a protection structure including a first wall portion and a second wall portion.

Trench power semiconductor and method of making the same

A manufacturing method of a chip package structure is provided. Firstly, a conductive frame including a bottom plate and a plurality of partition plates is provided. The bottom plate has a supporting surface and a bottom surface opposite thereto, and the partition plates protrude from the supporting surface to define a plurality of the accommodating regions. Subsequently, a plurality of chips is provided, and each of the chips is correspondingly accommodated in each of the accommodating regions with a back surface facing to the supporting surface. Thereafter, the conductive frame is cut to form a plurality of separated chip package structures.

Manufacturing method of a chip package structure

A manufacturing method of a trench power semiconductor device is provided. The manufacturing method includes the steps of forming a protective layer on an epitaxial layer and forming a trench gate structure in a trench formed in an epitaxial layer. The trench gate structure includes a shielding electrode, a gate disposed on the shielding electrode and an inter-electrode dielectric layer disposed therebetween. The step of forming the trench gate structure includes forming an insulating layer covering an inner surface of the trench; and before the step of forming the inter-electrode dielectric layer, forming an initial spacing layer, the spacing layer including a first sidewall portion and a second sidewall portion, both of which include bottom end portions spaced apart from each other and extending portions protruding from the protective layer.

Manufacturing method of a trench power semiconductor device

The present disclosure provides a trench power semiconductor component and a method of manufacturing the same. The trench gate structure of the trench power semiconductor component includes a shielding electrode, a gate electrode disposed above the shielding electrode, and an inter-electrode dielectric layer. Before the formation of the inter-electrode dielectric layer, the step of forming the trench gate structure includes: forming a laminated structure covering the inner wall surface of the cell trench, in which the laminated structure includes a semiconductor material layer and an initial inner dielectric layer covering the semiconductor material layer; forming a heavily-doped semiconductor material in the lower part of the cell trench; and removing a portion of the initial inner dielectric layer located at an upper part of the cell trench to expose an upper half portion of the semiconductor material layer and a top portion of the heavily doped semiconductor material.

The present disclosure provides a trench power semiconductor component and a method of making the same. The trench power semiconductor component includes a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is disposed on the substrate, the epitaxial layer having at least one trench formed therein. The trench gate structure is located in the at least one trench. The trench gate structure includes a bottom insulating layer covering a lower inner wall of the at least one trench, a shielding electrode located in the lower half part of the at least one trench, a gate electrode disposed on the shielding electrode, an inter-electrode dielectric layer disposed between the gate electrode and the shielding electrode, an upper insulating layer covering an upper inner wall of the at least one trench, and a protection structure including a first wall portion and a second side wall portion.

The present disclosure provides a trench power semiconductor component and a manufacturing method thereof. The trench gate structure of the trench power semiconductor component is located in the at least one cell trench that is formed in an epitaxial layer. The trench gate structure includes a shielding electrode, a gate electrode disposed above the shielding electrode, an insulating layer, an intermediate dielectric layer, and an inner dielectric layer. The insulating layer covers the inner wall surface of the cell trench. The intermediate dielectric layer interposed between the shielding electrode and the insulating layer has a bottom opening. The inner dielectric layer interposed between the shielding electrode and the intermediate dielectric layer is made of a material different from that of the intermediate dielectric layer, and fills the bottom opening so that the space of the cell trench beneath the shielding electrode is filled with the same material.

Trench power semiconductor device and manufacturing method thereof

A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.

Fan-out wafer level chip package structure

A super junction semiconductor device is provided. The super-junction semiconductor device includes a substrate, a drift layer disposed on the substrate, an insulating layer, a lightly-doped region, and a main loop-shaped field plate. The drift layer includes a plurality of n- and p-type doped regions alternately arranged in parallel to form a super-junction structure, and defines a cell region and a termination region surrounding the cell region. The lightly-doped region is formed in the drift layer and connected to a surface of the drift layer. The lightly-doped region has a first end portion closer to the cell region and a second end portion farther away from the cell region. The insulating layer disposed on the drift layer covers the termination region. The main loop-shaped field plate is disposed on the insulating layer and covers the second end portion.

Super-junction semiconductor device

A chip package structure and the manufacturing method thereof are provided. Firstly, a conductive frame including a bottom plate and a plurality of partition plates is provided. The bottom plate has a supporting surface and a bottom surface opposite thereto, and the partition plates protrude from the supporting surface to define a plurality of the accommodating regions. Subsequently, a plurality of chips is provided, and each of the chips is correspondingly accommodated in each of the accommodating regions with a back surface facing to the supporting surface. Thereafter, the conductive frame is cut to form a plurality of separated chip package structures.

Chip package structure and manufacturing method thereof

A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided, and one of the semiconductor devices has an active surface having an active region and an outer region and a back surface. A first electrode and a second electrode are arranged in the active region, and the outer region has a cutting portion and a channel portion. Subsequently, a trench is formed in the channel portion, and filled with a conductive structure. The wafer is fixed on a supporting board, and then a thinning process and a deposition process of a back electrode layer are performed on the back surface in sequence. Thereafter, the supporting board is removed and a plurality of contacting pads is formed. A cutting process is performed along the cutting portion.

Growing community of inventors

Hsinchu County, Taiwan

Hsiu-Wen Hsu