Via Technologies, Inc.

Advanced Micro Devices Corporation

Hsiu-Ming Chu

Kuan-Jui Ho

Ruei-Ling Lin

Chung-Che Wu

Kuang-Jui Ho

A computing system may implement a basic input/output system (BIOS) update method. The BIOS also includes identifying an installed central processing unit (CPU) of a computer system coupled to a BIOS chipset, selecting CPU firmware corresponding to the installed CPU from a plurality of CPU platform firmware stored on a first memory, and loading the CPU firmware into a shared portion of a second memory coupled to the BIOS chipset, where the shared portion of the second memory is configured to store the CPU firmware as secondary CPU firmware.

Combination BIOS with A/B recovery

In the described embodiments, a computing device executes firmware to perform a startup initialization operation, wherein performing the startup initialization operation comprises setting an operating state of a memory in the computing device to a default low performance memory operating state. After completing the startup initialization operation, the computing device executes an operating system, wherein executing the operating system comprises performing a memory test to determine a high performance memory operating state. The computing device then sets one or more memory configuration values based on the high performance memory operating state, the one or more memory configuration values controlling the operation of the memory.

Memory configuration operations for a computing device

A frequency working between the north bridge chip and random access memory of a computer system is dynamically and automatically adjusted in response to the frequency change of the CPU, in response to the workload of the north bridge chip or in response to the change of settings in a software program. The computer system may need to perform POST (Power-On Self Test) of BIOS to detect and calibrate the adjusted frequency.

Method for adjusting a frequency working between a north bridge chip and a random access memory of a computer system

A power-on method for a computer system comprising a processor supporting Hyper-Threading, a Read Only Memory (ROM) and a main memory, wherein the processor comprises a cache memory and the ROM comprises BIOS codes. The power-on method comprises the following steps. First, the processor is initialized in a Hyper-Threading disabled mode. The BIOS codes is then copied from the ROM to the cache memory, and the main memory is initialized by executing the BIOS codes therein. Thereafter, the processor is re-initialized in a Hyper-Threading enabled mode after the main memory is initialized. The processor comprises a first logic unit and a second logic unit. When initializing the processor, a first potential is applied to pin Aof the processor, and a reset signal is delivered to the processor while the pin Ais at the first potential, such that the processor is initialized in the Hyper-Threading disabled mode.

Power-on method for computer system that copies BIOS into cache memory of hyper-threading processor

A memory initialization method for a plurality of memories. The memories are initialized according to predetermined initial parameters. A first quantity of the memories is detected. Optimum parameters are set according hardware information of the memories. The memories are re-initialized according to the optimum parameters. A second quantity of the memories is detected. The parameters for memory initialization are adjusted when the first quantity and the second quantity are different.

Method for memory initialization involves detecting primary quantity of memories and setting optimum parameters based on hardware information of memories

A computer reset method activated by a South Bridge to directly reset a Central Processing Unit (CPU). First, a trigger signal is received. A CPU reset signal is delivered by the South Bridge when receiving the trigger signal. Thereafter, the CPU is reset when receiving the CPU reset signal from the South Bridge via a North Bridge.

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Taipei, Taiwan

Hsiu-Ming Chu