Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Hsiu-Jen Lin

Chung-Shi Liu

Ming-Da Cheng

Ching-Hua Hsieh

Wei-Yu Chen

Hao-Jan Pei

Chih-Chiang Tsao

Cheng-Ting Chen

Chih-Wei Lin

Chia-Shen Cheng

Chia-Lun Chang

Kuei-Wei Huang

Wei-Hung Lin

Hao-Yi Tsai

Chen-Hua Douglas Yu

Hsuan-Ting Kuo

Yu-Peng Tsai

Meng-Tse Chen

Philip Yu-Shuan Chung

Chun-Cheng Lin

Wen-Hsiung Lu

Jen-Jui Yu

Ai-Tee Ang

Cheng-Shiuan Wong

Tzu-Sung Huang

Hsien-Wei Chen

Chen-Shien Chen

Yen-Liang Lin

Chih-Hua Chen

Hung-Yi Kuo

Cheng-Chieh Hsieh

Yu-Chih Huang

Chung-Ming Weng

Chao-Wei Chiu

Ming-Hung Tseng

Tin-Hao Kuo

Yi-Wen Wu

Hui-Jung Tsai

Chih-Hsuan Tai

Bor-Ping Jang

Chien-Wei Lee

Ting-Ting Kuo

Chun-Ti Lu

Mirng-Ji Lii

Ming-Chih Yew

Ming-Che Ho

Chih-Hang Tung

Ming Hung Tseng

Sey-Ping Sun

Tsung-Hsien Chiang

Yu-min Liang

Yi-Jen Lai

Kuo-Lung Pan

Yang-Che Chen

Mao-Yen Chang

Yu-Tse Su

Chewn-Pu Jou

Chuei-Tang Wang

An-Jhih Su

Yu-Hsiang Hu

Kai-Chiang Wu

Tsung-Yuan Yu

Chung-Hao Tsai

Yu-Chia Lai

Hui-Min Huang

Sheng-Yu Wu

Yu-Min Liang

Cheng-Chung Lin

Chieh-Lung Lai

Zheng-Yi Lim

Jian-Shian Lin

Hua-Kuei Lin

Cheng-Tse Tang

Ming-Fa Chen

Kuo-Chung Yee

Sung-Feng Yeh

Chun-Lin Lu

Hsin-Yu Pan

Kuo Lung Pan

Tzu-Chun Tang

Po-Yuan Teng

Chia-Hung Liu

Ying-Cheng Tseng

Ban-Li Wu

Chao-Wei Li

Yu-Jen Tseng

Teng-Yuan Lo

Fang-Yu Liang

Tzong-Hann Yang

Yi-Ping Huang

Weng-Jung Lu

Tuan-Yu Hung

Jen-Chun Liao

Kris Lipu Chuang

Ting Hao Kuo

Cheng-Chieh Wu

Shau-Yi Chen

Ting-Hao Kuo

Chung-Cheng Lin

Tzong-Huann Yang

A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Package structure

A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

Semiconductor device and method of manufacture

An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Integrated circuit package and method

A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.

Integrated fan-out packages and methods of forming the same

A semiconductor package includes a substrate, a redistribution circuit layer, and a protective layer. The redistribution circuit layer is over the substrate and includes a plurality of functional pads electrically connected to the substrate, and a dummy pad pattern electrically disconnected from the plurality of functional pads, wherein the dummy pad pattern includes a plurality of pad portions connected to one another. The protective layer is disposed over the redistribution circuit layer and comprising a plurality of first openings spaced apart from one another and respectively revealing the plurality of pad portions.

Semiconductor package

A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.

Method of fabricating semiconductor structure

A method includes forming an insulating layer over a package. The package has a plurality of locations where openings are subsequently formed. A first laser shot is performed, location by location, on each of the locations across the package. A first laser spot of the first laser shot overlaps with each of the locations. The first laser shot removes a first portion of the insulating layer below the first laser spot. Another laser shot is performed, location by location, on each of the locations across the package. Another laser spot of the another laser shot overlaps with each of the locations. The another laser shot removes another portion of the insulating layer below the another laser spot. Performing the another laser shot, location by location, on each of the locations across the package is repeated multiple times, until desired portions of the insulating layer are removed.

Method for laser drilling process for an integrated circuit package

In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.

Methods of forming semiconductor packages

Provided is a package structure including a first redistribution layer (RDL) structure, a die, a circuit substrate, and a first thermoelectric cooler. The RDL) structure has a first side and a second side opposite to each other. The die is disposed on the first side of the first RDL structure. The circuit substrate is bonded to the second side of the first RDL structure through a plurality of first conductive connectors. The first thermoelectric cooler is between the first RDL structure and the circuit substrate, wherein the first thermoelectric cooler includes at least a N-type doped region and at least a P-type doped region.

Package structure having thermoelectric cooler

According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Substrate and package structure

A method of handling a workpiece includes the following steps. A workpiece is placed on a chuck body, wherein the workpiece includes a tape carrier extending beyond a periphery of the chuck body and a workpiece body disposed on the tape carrier, and the chuck body includes a seal ring surrounding the periphery of the chuck body; the tape carrier is clamped outside the chuck body, wherein the tape carrier leans against the seal ring and an enclosed space is formed between the chuck body, the tape carrier and the seal ring; and a vacuum seal is formed by evacuating gas from the enclosed space to pull the periphery of the workpiece toward the chuck body.

Method of manufacturing semiconductor package, method of handling wafer, and method of handling workpiece

A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.

Semiconductor package and method of forming the same

A package structure includes a die, an encapsulation layer, a redistribution layer structure and an adhesive material. The die includes a semiconductor substrate, conductive pads disposed over the semiconductor substrate and a passivation layer disposed over the semiconductor substrate and around the conductive pads. The encapsulation layer laterally encapsulates the die. the redistribution layer structure is disposed on the die and the encapsulation layer, and includes at least one redistribution layer embedded in at least one polymer layer, and the polymer layer contacts a portion of the passivation layer. The adhesive material is disposed on the die and covers an interface between the polymer layer and the passivation layer.

Package structure and method of forming the same

A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.

Semiconductor package and manufacturing method thereof

A package structure is provided. The package structure includes a semiconductor chip and a protective layer laterally surrounding the semiconductor chip. The package structure also includes a polymer-containing element over the protective layer. The protective layer is wider than the polymer-containing element.

Package structure with warpage-control element

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Zhubei, Taiwan

Hsiu-Jen Lin