International Business Machines Corporation

International Business Machines Cororation

HsinYu Tsai

Pritish Narayanan

Geoffrey W Burr

Robert L Bruce

Stefano Ambrogio

Hiroyuki Miyazoe

Matthew Joseph BrightSky

John M Papalia

Sanjay Kariyappa

Eugene John O'Sullivan

Cheng-Wei Cheng

Renee Tong Mo

Sufi Zafar

Eric Andrew Joseph

Nathan P Marchack

Ko-Tao Lee

Milos Stanisavljevic

Payel Das

Malte Johannes Rasch

Adam M Pyzyna

Pierce I-Jen Chuang

Shubham Jain

Karthik Yogendra

Charles Mackin

Mathieu Gallot

Embodiments disclosed herein include a compute in-memory (CIM) accelerator architecture for deep neural network (DNN). The CIM accelerator architecture may include a first analog fabric engine having a plurality of compute in-memory (CIM) analog tiles. Each CIM analog tile may be configured to store a matrix of weight operands producing a vector of outputs from a vector of inputs, and perform in-memory computations. The first analog fabric may also include a plurality of compute cores. Each CIM analog tile and each compute core may include a microcontroller configured to execute a set of instructions. The first analog fabric may also include on-chip interconnects communicatively connecting all CIM analog tiles in the plurality of CIM analog tile to the compute cores.

Two-dimensional mesh for compute-in-memory accelerator architecture

A method comprises receiving an input signal for processing in one or more neurons of a neural network, wherein the neural network has zero bias neurons and includes a plurality of resistive processing unit (RPU) weights and each neuron has an activation function. The method also includes applying an arbitrary amplification factor to activation function outputs of the one or more neurons in the neural network, wherein the arbitrary amplification factor is based on a dynamic range of components in the neural network and compensates for conductance drift in values of the RPU weights. The method also includes performing a calculation with the neural network using the amplified activation function outputs of the one or more neurons.

Neural network accelerators resilient to conductance drift

A computer implemented method for implementing a convolutional neural network (CNN) using a crosspoint array includes configuring the crosspoint array to implement a convolution layer by storing one or more weights in crosspoint devices of the array. The method further includes making multiple copies of the weights and training the CNN. Training the CNN includes mapping input data of the convolution layer to the crosspoint array in a row-by-row manner. Further the excitation is input in a row-by-row manner into the crosspoint array, thereby creating row-by-row forward output from the crosspoint array. Further, outputs from the crosspoint devices are stored to corresponding integrators. Errors in the outputs as compared to a desired output, from multiple rows are computed and back propagated in a row-by-row manner into the crosspoint array, the computed errors transmitted to a previous convolution layer.

Row-by-row convolutional neural network mapping for analog artificial intelligence network training

Implementing a convolutional neural network (CNN) includes configuring a crosspoint array to implement a convolution layer in the CNN. Convolution kernels of the layer are stored in crosspoint devices of the array. Computations for the CNN are performed by iterating a set of operations for a predetermined number of times. The operations include transmitting voltage pulses corresponding to a subpart of a vector of input data to the crosspoint array. The voltage pulses generate electric currents that are representative of performing multiplication operations at the crosspoint device based on weight values stored at the crosspoint devices. A set of integrators accumulates an electric charge based on the output electric currents from the respective crosspoint devices. The crosspoint array outputs the accumulated charge after iterating for the predetermined number of times. The accumulated charge represents a multiply-add result of the vector of input data and the one or more convolution kernels.

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

Drift regularization is provided to counteract variation in drift coefficients in analog neural networks. In various embodiments, a method of training an artificial neural network is illustrated. A plurality of weights is randomly initialized. Each of the plurality of weights corresponds to a synapse of an artificial neural network. At least one array of inputs is inputted to the artificial neural network. At least one array of outputs is determined by the artificial neural network based on the at least one array of inputs and the plurality of weights. The at least one array of outputs is compared to ground truth data to determine a first loss. A second loss is determined by adding a drift regularization to the first loss. The drift regularization is positively correlated to variance of the at least one array of outputs. The plurality of weights is updated based on the second loss by backpropagation.

Drift regularization to counteract variation in drift coefficients for analog accelerators

Methods and systems for performing calculations with a neural network include determining a conductance drift coefficient for resistive processing unit (RPU) weights in a neural network. A correction factor is applied to neuron inputs in the neural network in accordance with the drift coefficient and a time that has elapsed since the RPU weights were programmed. A calculation is performed with the neural network. The correction factor compensates for conductance drift.

Mitigation of conductance drift in neural network resistive processing units

A computer implemented method includes updating weight values associated with a plurality of analog synapses in a cross-bar array that implements an artificial neural network by sending a pulse sequence to the analog synapses. Each analog synapse includes a conductance unit, wherein a weight value of the analog synapse is based on a conductance value of the conductance unit. The pulse sequence changes the conductance value. The method further includes comparing the weight values of the analog synapses with target weight values associated with the analog synapses and selecting a set of analog synapses based on the comparison. The method further includes updating the weight values of the selected analog synapses by sending a set of electric pulses of varying durations.

Closed loop programming of phase-change memory

A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.

III-V CMOS co-integration

A method, computer program product, and system for identifying a surface area size of a biosensing structure, for use in a bionsensor device, based on a plurality of nucleotides structures under test. A first set of properties are determined comprising: reaction coordinate values, and potential of mean force (PMF) values, for the plurality of nucleotide structures based on a first set of testing conditions comprising a first surface area material, a first surface area pattern, and a first surface area size. A second set of properties is determined comprising reaction coordinate values, and PMF values, for the plurality of nucleotide structures based on a second set of testing conditions comprising a second surface area material, a second surface area pattern, a second surface area size, or a combination thereof and a target population of nucleotide structures among the plurality of nucleotide structures are identified.

Reduction of surface nucleotide hybridization by optimizing a biosensor sensing surface area

A process for forming patterned copper lines, a pattern of copper lines, and an electronic device having patterned copper lines and at least one CMOS circuit. The process includes assembling an etch stack, wherein the etch stack includes a resist and a copper substrate. The process also includes lithographically patterning the resist to produce a template, and forming a patterned block copolymer mask layer by directed self-assembly. Additionally, the process includes etching portions of the block copolymer mask layer to produce a patterned block copolymer mask layer, and transferring a pattern formed by the template and the patterned block copolymer mask layer to the copper substrate to form the patterned copper lines.

Directed self-assembly for copper patterning

A method of forming a semiconductor structure includes forming a first spacer material over two or more mandrels disposed over a magnetoresistive random-access memory (MRAM) stack. The method also includes performing a first sidewall image transfer of the two or more mandrels to form a first set of fins of the first spacer material over the MRAM stack, and performing a second sidewall image transfer to form a plurality of pillars of the first spacer material over the MRAM stack. The pillars of the first spacer material form top electrodes for a plurality of MRAM cells patterned from the MRAM stack.

Sidewall image transfer on magnetic tunnel junction stack for magnetoresistive random-access memory patterning

Embodiments of the invention are directed to methods and resulting structures for forming a storage element using phase change memory (PCM). In a non-limiting embodiment of the invention, a PCM layer is formed over a surface of a bottom electrode. A top electrode is formed over the PCM layer using a tone inversion process that includes a sacrificial layer. A PCM pillar is then formed by patterning the PCM layer to expose a surface of the bottom electrode. The tone inversion process enables a sub-50 nm PCM pillar diameter.

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San Jose, CA, United States of America

HsinYu Tsai