Mosel Vitelic Corporation

Vitelic Corporation

Hsing Ti Tuan

Li-Chun Li

Vei-Han Chan

Chung Wai Leung

Chia-Shun Hsiao

Thomas Tong-Long Chang

Michael A Murray

Lynne Hannah

Chung-Wai Leung

A nonvolatile memory array can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells of the array in parallel.

Nonvolatile memory structures and fabrication methods

Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

Dummy structures that protect circuit elements during polishing

In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Nonvolatile memory structures and access methods

In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask ( ) is used to remove the select gate layer from over the source lines ( ), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

In a nonvolatile memory, a floating gate includes a portion of a conductive layer ( ), and also includes conductive spacers ( ). The spacers increase the capacitive coupling between the floating gate and the control gate ( ).

Nonvolatile memories with floating gate spacers, and methods of fabrication

A logical latch is permanently programmable to a selected state for use as a control circuit with extremely low power consumption in an integrated circuit.

Programmable circuit with fusible latch

An integrated circuit memory device is provided which includes a memory array including multiple memory cores, each core including a two-dimensional (x,y) array of memory cells, the memory array further including a plurality of x-lines and a plurality of y-lines; an address bus including a first bus oriented with a y-dimension and a second bus oriented with an x-dimension; and x-address generator; a y-address generator; a multiplexer circuit for operatively coupling one of the x-address generator and the y-address generator to the address bus; a plurality of y-address decoders each for producing decoded y-information to at least one of the plurality of y-lines; a plurality of separate x-address decoders each for producing decoded x-information for at least one of the plurality of x-lines; and a plurality of separate sustain circuits each for sustaining decoded x-information produced by at least one x-decoder.

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Cupertino, CA, United States of America

Hsing Ti Tuan