Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsing-Lien Lin

Cheng-Yuan Tsai

Hai-Dang Trinh

Chia-Shiung Tsai

Fa-Shen Jiang

Chii-Ming M Wu

Yao-Wen Chang

Chin-Wei Liang

Bi-Shen Lee

Hsun-Chung Kuang

Wen-Ting Chu

Yeur-Luen Tu

Trinh Hai Dang

Jian-Shiou Huang

Yi Yang Wei

Chung-Yi Yu

Jung-Huei Peng

Yuan-Chih Hsieh

Yi-Chien Wu

Rei-Lin Chu

Ching Ju Yang

Yu-Jen Wang

Chin-Chieh Yang

Chih-Ta Wu

Yu-Wen Liao

Ru-Liang Lee

Han-Chin Chiu

Chung Chien Wang

Chern-Yow Hsu

Lan-Lin Chao

Fu-Ting Sung

Kai-Wen Cheng

Chi-Hsin Lo

Yuan-Hung Liu

Tzu-Chung Tsai

Cheng-Te Lee

Jason Lee

Cheng-Ta Wu

Hsia-Wei Chen

Xiaomeng Chen

Wen-Chuan Chiang

Kuo-Yin Lin

Tzu-Yu Lin

Chia-Lin Chen

Tsung-Hsun Huang

Huey-Chi Chu

Ming-Chih Tsai

Jui-Lin Chu

Hsin-Yu Lai

Wei-Min Tseng

Lucy Chang

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode structure disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. The bottom electrode structure has an upper surface including a noble metal. A diffusion barrier layer is over the bottom electrode structure, a data storage structure is over the diffusion barrier layer, and a top electrode structure is over the data storage structure. The diffusion barrier layer is configured to mitigate a diffusion of noble metal atoms from the bottom electrode structure to the data storage structure.

RRAM structure

A semiconductor device structure is provided. The structure includes a substrate and a data storage element over the substrate. The structure also includes a protective element extending into the data storage element. A bottom surface of the protective element is between a top surface of the data storage element and a bottom surface of the data storage element. The structure further includes a first electrode electrically connected to the data storage element and a second electrode electrically connected to the data storage element.

Memory device structure with data storage element

Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Method to reduce breakdown failure in a MIM capacitor

Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.

Resistive memory cell with switching layer comprising one or more dopants

A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

FeRAM with laminated ferroelectric film and method forming same

A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.

Capacitor structure and method of making the same

The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode disposed over a substrate and a second electrode over the first electrode. A doped data storage structure is disposed between the first electrode and the second electrode. The doped data storage structure has a dopant with a doping concentration profile that is asymmetric over a height of the doped data storage structure and that has a maximum dopant concentration at non-zero distances from a top surface and a bottom surface of the doped data storage structure.

RRAM device with improved performance

An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.

Techniques to inhibit delamination from flowable gap-fill dielectric

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A dielectric layer is formed on the bottom electrode. A first top electrode layer is deposited on the dielectric layer by a first deposition process. A diffusion barrier layer is deposited on the first top electrode layer by a second deposition process different from the first deposition process. A second top electrode layer is deposited on the diffusion barrier layer by a third deposition. The third deposition process is the same as the first deposition process.

Diffusion barrier layer in top electrode to increase break down voltage

Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.

Resistive memory cell having a low forming voltage

A method for forming a semiconductor structure includes following operations. A first conductive layer is formed. A first dielectric layer is formed over the first conductive layer, and the first dielectric layer includes at least one trench exposing the first conductive layer. A second conductive layer is formed in the trench. A third conductive layer is formed in the trench, and a resistivity of the third conductive layer is greater than a resistivity of the second conductive layer. A second dielectric layer is formed over the third conductive layer. A phase change material is formed over the first dielectric layer.

Method for forming semiconductor structure

The present disclosure provides a structure and method of fabricating the structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.

Semiconductor MEMS structure

Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

MIM capacitor with a symmetrical capacitor insulator structure

A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.

Semiconductor device and method for manufacturing the same

A method for forming a semiconductor memory structure include forming a pillar structure. The pillar structure includes a first conductive layer, a second conductive layer and a data storage material layer between the first and second conducive layers. A sidewall of the first conductive layer, a sidewall of the data storage layer and a sidewall of the second conductive layer are exposed. An oxygen-containing plasma treatment is performed on the pillar structure to form hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer. An encapsulation layer is formed over the pillar structure and the dielectric layer. The encapsulation layer is in contact with the hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer.

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Hsin-Chu, Taiwan

Hsing-Lien Lin