Western Digital Technologies, Inc.

Hsing Heng Hsieh

Dar-Der Chang

John Randall

Victor Avila

Charles Dominic Potter

Aspects of a storage device including a memory and a controller are provided for error detection and data integrity checking during the data transfer of write operations. The memory includes a write enable input. The controller generates data integrity information based on at least one data byte to be written to the memory, and transfers the at least one data byte and the data integrity information to the memory, with the data integrity information being transferred to the write enable input. A data integrity circuit receives the at least one data byte and the data integrity information from the controller, and detects whether an error exists in the at least one data byte based on the data integrity information. Accordingly, error detection of data being written to memory may be improved by the data integrity checking of the data prior to being written to the memory of the storage device.

Data integrity check for writing data in memory

In some examples, a method includes assigning, to each respective task queue of a plurality of task queues, a respective priority ratio based at least in part on a number of tasks in the respective task queue. The method further includes assigning, by a processor of a plurality of processors, respective tasks from the respective task queues to at least one processor of the plurality of processors in an order based at least in part on the respective priority ratio, wherein the respective priority ratio defines a relative frequency with which tasks from the respective task queue are assigned to the at leak one processor.

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San Jose, CA, United States of America

Hsing Heng Hsieh