Texas Instruments Corporation

Other

Hsindao E Lu

Terence G Blake

Theodore Warren Houston

Weider Peter Chang

Fan Zhai

A method and apparatus for ringing artifacts reduction for compressed video signals. The method includes receiving luma data to the digital signal processor, calculating sum of gradient of the luma data; calculating SAD of the luma data; performing pixel classification based of the calculated SAD and sum of gradient, performing erosion on a detected edge pixel indicator on a detected flat pixel indicators, determining at least one of the strength or weakness of the an edge based on the determined edge erosion, performing horizontal dilation on the detected edge pixel indicators and edge strength; and performing at least one of sigma or bilateral filtering to the luma data according to the detected edge pixel indicator, flat pixel indicator, edge strength, the number of very flat pixel in the block.

Method and apparatus for reducing ringing artifacts

The write circuit for SRAM memories of this invention includes on each column select line B1,B1' a N-type transistor (N1, N2) which is utilized to drive the voltage on one of the column select lines to V.sub.cc -V.sub.t. A pull-up circuit circuit is also provided with each column select line B1, B1'which includes a P-type transistor (P1,P2) which is coupled to the supply V.sub.cc. This circuit raises the voltage which appears between the two column select lines B1, B1' to V.sub.cc which is used to write data to a SRAM cell 10, 12 disposed therebetween.

Bit lines write circuit for SRAM memories

A tristateable sense amplifier, for driving a bus directly with minimal size devices, includes a control transistor coupled to a reference voltage terminal and having a control electrode receiving a first control signal. A first series circuit includes a first transistor of a first channel type and a second transistor of opposite channel type coupled between the control transistor and a supply voltage terminal. A control electrode of the second transistor receives a first input signal and the second transistor generates a first output signal. A second series circuit includes a third transistor of the first channel type and a found transistor of the opposite channel type coupled between the control transistor and the supply terminal. A second input signal is coupled to the control electrode of the fourth transistor. A fifth transistor of the first channel type is coupled between the voltage supply terminal and the control electrodes of the first channel type transistors and has a control electrode coupled to receive a second control signal. A sixth transistor of the first channel type is coupled between the control electrodes of the first channel type transistors and a junction of the third and fourth transistors and has a control electrode coupled to receive a third control signal.

Tri-stateable current mirror sense amplifier

An on-chip transient event detector (FIG., 1) is fabricated onto an integrated circuit chip to provide rapid response to a detected event, such as a transient radiation dose or other condition that can cause transient current pulses. The transient event detector includes a detector circuit 10 that includes a narrow p-channel FET (12), and a wide n-channel FET (14). These detector transistors are coupled together and biased so that the narrow-channel transistor is normally on and the wide-channel transistor is normally off. A transient event, such as a photocurrent induced by radiation, causes a current pulse in the normally off wide-channel transistor that is sufficiently greater than the current in the narrow-channel transistor to cause a change in logic output, providing an event signal. The event signal can be used to disable memory WRITE operations during the transient event. The detector circuit can be integrated with an on-chip time-delay circuit (30) to provide a time-delayed system reset signal.

On-chip transient event detector

A floating body field effect transistor having a defined breakdown voltage, and a lower holding voltage, serves to clamp electrostatic discharge voltages to a low voltage level, thereby minimizing thermal power dissipation within the thin semiconductor layer of semiconductor-on-insulator circuits.

ESD protection for SOI circuits

A process for making a silicon-on-insulator MOS transistor is disclosed which includes forming an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to sidewall oxide filaments on the source side of the gate electrode. The lightly-doped drain extension of the source region remains disposed between the contact region and the body node at the surface, but the contact region extends below the depth of the lightly-doped drain region to make contact to the body node. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor. For SOI CMOS technology, no additional photolithographic or implant steps are required for formation of the contact, as the source/drain implant masks required for the masking of opposite conductivity type regions and the associated implants can be used in the formation of the contact region.

Process for making high performance silicon-on-insulator transistor with

A silicon-on-insulator MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to sidewall oxide filaments on the source side of the gate electrode. The lightly-doped drain extension of the source region remains disposed between the contact region and the body node at the surface, but the contact region extends below the depth of the lightly-doped drain region to make contact to the body node. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor. For SOI CMOS technology, no additional photolithographic or implant steps are required for formation of the contact, as the source/drain implant masks required for the masking of opposite conductivity type regions and the associated implants can be used in the formation of the contact region.

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Dallas, TX, United States of America

Hsindao E Lu