Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Hsin-Yu Lai

Katherine H Chiang

Kuo-Chi Tu

Hsing-Lien Lin

Hai-Dang Trinh

Hsun-Chung Kuang

Sheng-Hung Shih

Tzu-Yu Chen

Fu-Chen Chang

Bi-Shen Lee

Cheng-Hsien Liu

Yi Yang Wei

Hui-Ling Lin

Chen-Wei Wu

Chau-Ting Yeh

Tzu-Chi Yu

A method for fabricating a semiconductor device is provided. The method includes depositing a ferroelectric layer over the substrate; performing a first ionized physical deposition process to deposit a top electrode layer over the ferroelectric layer; patterning the top electrode layer into a top electrode; and patterning the ferroelectric layer to into a ferroelectric element below the top electrode.

Method of fabricating semiconductor device comprising ferroelectric layer

A method for manufacturing a stacked capacitor structure includes: forming a first patterned structure over a substrate; forming a first bottom electrode over the first patterned structure; depositing a first dielectric film over the first bottom electrode; depositing a first top electrode layer over the first dielectric film; forming a first vertical interconnect structure; forming a second patterned structure over the first top electrode layer; forming a second bottom electrode over the second patterned structure and electrically connected to the first bottom electrode through the first vertical interconnect structure; depositing a second dielectric film over the second bottom electrode; depositing a second top electrode layer over the second dielectric film; and forming a second vertical interconnect structure extending from the first top electrode layer. The second top electrode layer is electrically connected to the first top electrode layer through the second vertical interconnect structure.

Stacked capacitor structure and manufacturing method thereof

A capacitor structure, a method for manufacturing a capacitor structure and a method for operating a capacitor structure are provided. The capacitor structure includes a first electrode and a second electrode; a dielectric layer between the first electrode and the second electrode; and an oxygen donor layer between the dielectric layer and the first electrode. An oxygen concentration of the oxygen donor layer increases along a thickness direction from a first surface proximal to the dielectric layer to a second surface proximal to the first electrode.

Capacitor structure and manufacturing method and operating method thereof

Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.

Multi-layer electrode to improve performance of ferroelectric memory device

Disclosed is a microfluidic chip and method using the same. The microfluidic chip comprises a substrate having a surface, and at least a tissue culture area formed on the surface of the substrate. The tissue culture area has a microfluidic channel formed by a plurality of connected geometrical structures (nozzle-type channels) having a predetermined depth. The microfluidic channel has an inlet and an outlet, which are at two ends of the microfluidic channel, for medium inputting and outputting, respectively. Additionally, at least an air-exchange hole is formed on the bottom of the microfluidic channel. By using the microfluidic chip for tissue culture, lateral flow speed and stress can be decreased, so as to prolong survival time of tissues (e.g. liver tissues).

Microfluidic chip and method using the same

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Hsinchu, Taiwan

Hsin-Yu Lai