Taiwan Semiconductor Manufacturing Comp. Ltd.

Acer Inc.

Quanta Computer Incorporated

Delta Electronics, Inc.

Aspeed Technology Inc.

Other

National Yang Ming Chiao Tung University

Dexatek Technology Ltd.

Xinadda Inc.

Hsin-Yu Chen

Wen-Chih Chiou

Tsang-Jiuh Wu

Ku-Feng Yang

Yung-Chi Lin

Jui-Chun Weng

Lin-Chih Huang

Hsi-Cheng Hsu

Ji-Hong Chiang

Wei-Ding Wu

Han-Zong Pan

You-Cheng Jhang

Ming-Tsu Chung

Tasi-Jung Wu

Ching-Hsiang Hu

Jing-Cheng Lin

Hong-Ye Shih

Shyh-Wei Cheng

Lavanya Sanagavarapu

Chia-Chun Hung

Kuo-Hao Lee

Chia-Yin Chen

Hsiao Yun Lo

HsiaoYun Lo

Yuan-Hung Liu

Fang Wen Tsai

Jia-Syuan Li

Chun-Peng Li

Jiun-Jie Chiou

Shin-Hua Chen

Chih-Yu Wang

Jian-Wei Lee

Jun-Liang Lu

Yen-Chiang Liu

Chen-Hua Douglas Yu

Shin-Puu Jeng

Po-Hao Tsai

Cheng-Lin Huang

Cheng-Chieh Hsieh

Chung-Yen Lu

Tzu-Heng Chang

Chin-Min Lin

Sheng-Yuan Lin

Chen-Yu Tsai

Chiu-Hua Chung

Hsin Chang

Tien-Szu Lo

Po-Wei Wu

Meng-Seng Chen

Chung-Te Li

Yan-Fu Lin

Hung-An Teng

Jiung Wu

Chen-Kang Su

Keng-Sheng Lin

Pei-Ching Kuo

Li-Yang Tu

Cheng-San Chou

Ya-Hsi Hwung

Hung-Chi Chen

Chueh-Pin Ko

Jong Chen

Hsin-Yi Tsai

Wen-Chu Yang

Cheng-Yi Hsu

Ling-Fan Tsao

Yu-Jui Wu

Tz-Yu Fu

Ming-Tsung Chen

Chia-Yu Lin

Han Tsung Chen

Pin-Hsin Chang

Ta-Wei Chang

Chih-Chi Cheng

Jung-Chih Chen

Hao-Jen Wang

Chuan-Yi Ko

Hsung-Pin Chang

Sheng-Hung Cheng

Huei-Shiang Chien

I-Chiu Li

Kun-Che Li

Ching-Cheng Chuang

Mei-Lan Ko

Chia-Hsuan Chang

Yen Chiang Liu

Chien-Tai Su

Yen-Chieh Tu

Jiu-Chun Weng

Ming-Yu Chien

Long-Wen Chen

Chin-An Lin

Ping-Han Chen

Chung-Hsien Hung

Chih-Hsien Chen

Yu-Mei Wu

Shuo-Li Shih

Bing-Chia Peng

Chien-Chih Hsu

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Semiconductor device having backside interconnect structure on through substrate via

A system for detecting usage and position of a height adjustable work surface is disclosed that includes a smart hub device that uses a set of sensors to collect sensor data to determine whether a work area is occupied or unoccupied, and to also collect work area usage data for further analysis regarding the details of usage of the work area.

System for detecting usage and position of a height adjustable work surface

Systems and methods are provided for fail-safe protection of circuitry from electrostatic discharge due through input and output connections. The power circuitry may include a string of diodes, connections to power lines, and particular diodes for voltage pull-up and pull-down clamping. There may be both a pull-up third diode in the diode string for connection between I/O and VDD and a pull-down third diode between I/O and VSS. During an ESD event the ESD device is configured to hold voltage from exceeding a threshold voltage and damaging internal circuitry. During operational mode the ESD device is turned off and does not interfere with circuit operations.

Failsafe input/output electrostatic discharge protection with diodes

Optical sensors and their making methods are described herein. In some embodiments, a described sensing apparatus includes: an image sensor; a collimator above the image sensor, wherein the collimator includes an array of apertures; and an optical filtering layer above the collimator, wherein the optical filtering layer is configured to filter a portion of light to be transmitted into the array of apertures.

Optical sensor and methods of making the same

Method of forming semiconductor device having backside interconnect structure on through substrate via

The present disclosure provides electrostatic discharge circuits and structures and methods for operating the electrostatic discharge circuits and structures. A circuit includes a first transistor and a second transistor. The first transistor includes a drain, a source, a gate, and a bulk. The drain of the first transistor is connected to a first terminal. The source of the first transistor is connected to receive a first voltage. The gate and the bulk of the first transistor is connected to receive a second voltage. The second transistor includes a drain, a source, a gate, and a bulk. The source, the gate, and the bulk of the second transistor is connected to receive the second voltage. The drain of the second transistor is connected to the first terminal. In response to the terminal reaching a trigger voltage, the first transistor is configured to be turned on.

Electrostatic discharge circuits and methods for operating the same

A portion of a buffer layer on a backside of a substrate of a photomask assembly may be removed prior to formation of one or more capping layers on the backside of the substrate. The one or more capping layers may be formed directly on the backside of the substrate where the buffer layer is removed from the substrate, and a hard mask layer may be formed directly on the one or more capping layers. The one or more capping layers may include a low-stress material to promote adhesion between the one or more capping layers and the substrate, and to reduce and/or minimize peeling and delamination of the capping layer(s) from the substrate. This may reduce the likelihood of damage to the pellicle layer and/or other components of the photomask assembly and/or may increase the yield of an exposure process in which the photomask assembly is used.

Photomask assembly and method of forming the same

Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction.

Multifunctional collimator for contact image sensors

A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.

Through via structure and method

Alignment of devices formed on substrates that are to be bonded may be achieved through the use of scribe lines between the devices, where the scribe lines progressively increase or decrease in size from a center to an edge of one or more of the substrates to compensate for differences in the thermal expansion rates of the substrates. The devices on the substrates are brought into alignment as the substrates are heated during a bonding operation due to the progressively increased or decreased sizes of the scribe lines. The scribe lines may be arranged in a single direction in a substrate to compensate for thermal expansion along a single axis of the substrate or may be arranged in a plurality of directions to compensate for actinomorphic thermal expansion.

Wafer bonding alignment

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

Interconnect structure and method of forming same

Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1&#xd7;10per cubic centimeter (cm) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.

A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.

Pellicle frame with stress relief trenches

A polyhedron lens architecture is disposed in a virtual sphere. The virtual sphere has a horizontal plane, an upper hemisphere above the horizontal plane and a lower hemisphere below the horizontal plane. The polyhedron lens architecture has an upper half part above the horizontal plane, and a lower half part below the horizontal plane. The polyhedron lens architecture includes: multiple bases, which are respectively disposed on the upper half part and the lower half part; and multiple lenses respectively disposed on surfaces of the bases. Optical axes of the lenses intersect at a central point, which is located at the horizontal plane and is a structural center of the polyhedron lens architecture.

Polyhedron lens architecture and lens scanning method suitable for the polyhedron lens architecture

An electronic device coupled to a display includes a graphics card and a processor. The graphics card reads the extended display identification data from the display. The processor determines, according to the extended display identification data, that the display is able to display a default resolution at a first refresh rate at most, and determines, according to the extended display identification data, whether the display device is able to display the default resolution at a second refresh rate that exceeds the first refresh rate. When it is determined that the display is able to display the default resolution at the second refresh rate, the processor adds the second refresh rate into the extended display identification data.

Electronic device, display method, and machine-readable storage medium for determining the margin of a display for overclocking

Growing community of inventors

Taipei, Taiwan

Hsin-Yu Chen