Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsin Yang Hung

Tsung-Yu Chiang

Wei-Yen Woon

Lung Chen

Szuya Liao

Ku-Feng Yang

Che Chi Shih

Wei-Syuan Dai

Semiconductor structure and methods of forming the same are provided. A semiconductor structure according to the present disclosure include a substrate that includes a first region and a second region adjacent the first region, a first fin disposed over the first region, a second fin disposed over the second region, a first source/drain feature disposed over the first fin and a second source/drain feature disposed over the second fin, and an isolation structure disposed between the first fin and the second fin. The isolation structure has a protruding feature rising above the rest of the isolation structure and the protruding feature is disposed between the first fin and the second fin.

Reduction of damages to source/drain features

A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed. A contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.

Selective epitaxy process for the formation of CFET local interconnection

Growing community of inventors

Hsinchu, Taiwan

Hsin Yang Hung