Anpec Electronics Corporation

Hsin-Tai Lin

Chih-Yuan Chen

Tzu-Yang Yen

A power converter with a negative current detection mechanism is provided. A negative current detecting circuit includes a first operational amplifier, a first transistor and a second transistor. A non-inverting input terminal of the first operational amplifier is connected to a second terminal of a sense resistor. An inverting input terminal of the first operational amplifier is connected to a first terminal of a first capacitor. Control terminals of the first and second transistors are connected to an output terminal of the first operational amplifier. A first terminal of the first transistor is connected to the second terminal of the sense resistor. A second terminal of the first transistor is grounded. A first terminal of the second transistor is connected to the inverting input terminal of the first operational amplifier and the first terminal of the first transistor. A second terminal of the second transistor is grounded.

Power converter having negative current detection mechanism

A multi-phase DC-DC power converter includes an error amplifier, a comparator, a phase selection circuit, a plurality of phase circuits and a width detecting circuit. The plurality of phase circuits are each associated with a phase of the multi-phase DC-DC power converter, each including a turn-on clock generation circuit, a first switching transistor, a second switching transistor, an output inductor, and a control logic. In a load transition state, when the width detecting circuit detects that a comparison output signal exceeds a predetermined width, the phase selection circuit adjusts one of the plurality of phase signals based on a force trigger signal, and outputs, corresponding to a force trigger signal, one of the plurality of on-signals.

Multi-phase DC-DC power converter and driving method of the same

A system and a method for improving continuous load transition of a DC-DC converter are provided. The system includes a conduction detector circuit, a counter circuit, a depth control circuit and a slope generator. The conduction detector circuit detects a phase signal of the DC-DC converter to generate a pulse signal. The counter circuit counts the number of pulse waves of the pulse signal to output a counting signal. The depth control circuit generates a pulled-down depth signal. The slope generator generates a slope signal according to the pulled-down depth signal. The pulled-down depth signal is pulled down by a first depth each time the switch circuit is conducted, but when the number of times that the switching circuit is conducted reaches a conduction number threshold, the pulled-down depth signal is pulled down by a second depth that is larger than the first depth.

System and method for improving continuous load transition of DC-DC converter

A multi-phase DC-DC power converter includes an error amplifier, a comparator, a phase selection circuit, a plurality of phase circuits and a PFM/PWM logic control circuit. The plurality of phase circuits are each associated with a phase of the multi-phase DC-DC power converter, each including a turn-on clock generation circuit, a first switching transistor, a second switching transistor, an output inductor, a zero-crossing detection circuit, and a control logic. The PFM/PWM logic control circuit is configured to output, in response to a PFM control signal and a control signal associated with switch signals, a first PFM control signal and a second PFM control signal to a first phase circuit and a second phase circuit of the plurality of phase circuits. The PFM/PWM logic control circuit enters a first phase, a second phase, and a third phase under a light load condition or a no load condition.

Disclosed are an operational amplifier and a method for reducing an offset voltage of the operational amplifier, which control an auxiliary circuit to generate a first auxiliary current and a second auxiliary current by adjusting the resistance of a resistance regulator, thereby adjusting a first current and a second current outputted from an input-stage circuit and further adjusting the offset voltage of the operational amplifier. Therefore, the operational amplifier and the method for reducing the offset voltage of the operational amplifier use the resistors to adjust the offset voltage so as to reduce the Least Significant Bit (LSB) distribution, thereby enhancing the accuracy of the offset voltage.

Operational amplifier and method for reducing offset voltage of operational amplifier

The present disclosure provides a constant on-time converter having fast transient response, which adaptively adjusts an on-time and an off-time by a first compensation circuit and a second compensation circuit, to accordingly adjust an inductive current. When a load converts a light loading into a heavy loading, the constant on-time converter adaptively adjusts the on-time of the clock signal. When the load converts a heavy loading into a light loading, the constant on-time converter adaptively adjusts the off-time of the clock signal. Therefore, the output voltage can be adjusted rapidly in response to different load changes to enhance the transient response of the output voltage.

Constant on-time converter having fast transient response

A current mode voltage converter having fast transient response is provided. The current mode voltage converter is used for converting an input voltage into an output voltage to drive a load. The current mode voltage converter adaptively adjusts the frequency of a clock signal by a first compensation circuit and a second compensation circuit to accordingly adjust an inductive current. Therefore, the output voltage can be adjusted rapidly in response to different load changes to enhance the transient response of the output voltage.

Current mode voltage converter having fast transient response

A modulation method, for a voltage converting device, includes generating a first modulation signal according to an input voltage and a first output voltage; generating a second modulation signal according to the input voltage and a second output voltage; adjusting the first modulation signal and the second modulation signal according to a clock signal for making a first starting time of the first modulation signal be different from a second starting time of the second modulation signal; and generating the first output voltage and the second output voltage according to the input voltage, the first modulation signal and the second modulation signal.

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Taichung, Taiwan

Hsin-Tai Lin