United Microelectronics Corp.

Untied Microelectronics Corp.

Hsin-Ming Hou

Ji-Fu Kung

Yu-Cheng Tung

Wai-Yi Lien

Ming-Tsung Chen

An insulated gate bipolar transistor includes a P-type group III-V nitride compound layer. An N-type group III-V nitride compound layer contacts a side of the P-type group III-V nitride compound layer. An HEMT is disposed on the N-type group III-V nitride compound layer. The HEMT includes a first group III-V nitride compound layer disposed on the N-type group III-V nitride compound layer. A second group III-V nitride compound layer is disposed on the first group III-V nitride compound layer. A source is embedded within the second group III-V nitride compound layer and the first group III-V nitride compound layer, wherein the source includes an N-type group III-V nitride compound body and a metal contact. A drain contacts another side of the P-type group III-V nitride compound layer. A gate is disposed on the second group III-V nitride compound layer.

Insulated gate bipolar transistor

For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

Hierarchical wafer lifetime prediction method

A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.

Semiconductor device with epitaxial structures and method for fabricating the same

A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure. The first semiconductor substrate comprises a first substrate portion and a first conductive layer on an active surface of the first substrate portion. The second semiconductor substrate comprises a second substrate portion and a second conductive layer on an active surface of the second substrate portion. The trench passes through the second substrate portion and exposing the second conductive layer. The via passes through the dielectric layer and exposes the first conductive layer. The conductive structure has an upper portion filling the trench and a lower portion filling the via. Opposing side surfaces of the upper portion are beyond opposing side surfaces of the lower portion.

Stacked semiconductor structure and manufacturing method for the same

Semiconductor device and method for fabricating the same

A multi-gate transistor device includes a substrate, a fin structure extending along a first direction formed on the substrate, a gate structure extending along a second direction formed on the substrate, a drain region having a first conductivity type formed in the fin structure, a source region having a second conductivity type formed in the fin structure, and a first pocket doped region having the first conductivity type formed in and encompassed by the source region. The first conductivity type and the second conductivity type are complementary to each other.

Multi-gate transistor device

Hierarchical wafer yield prediction method and hierarchical lifetime prediction method

A wafer fabrication outcome, such as wafer yield or wafer lifetime, is predicted by excluding uncontrollable but measurable internal/external noises of a DOE system, and by rendering relations between wafer design variables and wafer outcome outputs to be more causal, as well as the relations between variances for each of the wafer design variables and the wafer outcome outputs. With the aid of a wafer fabrication outcome predicting model formed by the more causal relations, precision of predicting wafer outcomes can be raised, and performance of wafer fabrication can be thus raised as a result.

Experiments method for predicting wafer fabrication outcome

A layout correcting method and a layout correcting system are provided. The layout correcting method includes the following steps. An integrated circuit design layout is provided. A plurality of performance parameters of the integrated circuit design layout are analyzed. A plurality of devices under test is selected according to the performance parameters. A computer simulating process is performed on the devices under test and a direct probing process is performed on the devices under test. The direct probing process is an on-chip test for comparing each device under test and an environment condition thereof by a Boolean algebra algorithm. A plurality of differences between the results of the computer simulating process and the direct probing process is analyzed. The integrated circuit design layout is corrected according to differences between the results of the computer simulating process and the direct probing process.

Layout correcting method and layout correcting system

A transistor array for testing is provided. The transistor array includes a plurality of tested units. Each of the tested unit includes a tested transistor and a first to third switches. The tested transistor has a control terminal, a first and a second terminals and a bulk. The first switch is coupled between the first terminal and a leakage transporting line. The second switch is coupled between the second terminal and the leakage transporting line. The third switch is coupled between the control terminal and a bias providing line. The first to third switches are turned on or turned off according to a control signal. When the tested transistor is selected to be tested, the first to third switches are turned on according to the control signal.

Transistor array for testing

An integrated circuit design and fabrication method includes the following steps. Firstly, an integrated circuit design layout is provided. Then, a first hotspot group and a second hotpot group are searched from the integrated circuit design layout. Then, a hotspot score is acquired according to the first hotspot group, the second hotpot group and a product functionality. If the hotspot score is higher than a criterion, the integrated circuit design layout is corrected according to the first hotspot group and the second hotpot group.

Integrated circuit design and fabrication method by way of detecting and scoring hotspots

A layout of dummy patterns on a wafer having a plurality of pads disposed thereon is described. The layout of the dummy patterns includes having a plurality of dummy patterns spaced apart from each other and enclosing the plurality of the pads. The plurality of dummy patterns also include a plurality of peripheral dummy patterns and a plurality of central dummy patterns, wherein a minimum distance between the plurality of the central dummy patterns and the plurality of the pads is greater a minimum distance between the plurality of the peripheral dumpy patterns and the plurality of the pads.

Layout of dummy patterns

A method of disposing dummy patterns is described, which is used for increasing the pattern density of an aluminum pad layer. A substrate is provided, and an aluminum pad material layer is formed on the substrate. Then, the aluminum pad material layer is patterned to form the aluminum pad layer which includes a plurality of aluminum pads and a plurality of dummy patterns, wherein the dummy patterns are distributed in the spaces between the aluminum pads. Besides, routings can be further disposed in the aluminum pad layer and the dummy patterns are distributed in the spaces between the aluminum pads, between the aluminum pads and the routings, or between the routings.

Growing community of inventors

Tainan, Taiwan

Hsin-Ming Hou