United Microelectronics Corp.

Au Optronics Corporation

Brillnics Singapore Pte. Ltd.

Hsin-Li Chen

Yu-Min Lin

Feng-Yuan Gan

Te-Sun Wu

Wood Wu

Stephen S Fu

Han-Shen Lo

Hung-Lung Hsu

Kai-Chi Hsieh

Yulin Tsai

Yue-Hsian Lin

Disclosure herein relates to a unit pixel structure incorporating multiple photodiodes is disclosed. The unit pixel is formed in a semiconductive stack. The unit pixel includes a sensor well region, a floating diffusion region, a first gate structure and a second gate structure. The first gate structure is disposed over the semiconductive stack and the second gate structure extends into the semiconductive stack.

Pixel structure for image sensors

A backlight module and a display module are provided. The backlight module includes a back frame, a light guide plate, a heat sink, a light source module and a carrying frame. The light guide plate has a light emitting top surface and a light incident side surface, and is disposed on the back frame. The heat sink is disposed between the back frame and the light guide plate, and a side surface of the heat sink has a first fixing portion exposed outside the back frame. The light source module is disposed on the heat sink and faces the light incident side surface of the light guide plate. The carrying frame includes a first side wall, and is disposed around the light guide plate. The first side wall has a second fixing portion engaged with the first fixing portion, and is located outside the back frame.

Backlight module and display module

A photo detector and related fabricating method are disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer. The patterned conductive layer is disposed on the dielectric layer. The inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region. The first electrodes are electrically connected to the first patterned semiconductor layer.

Method for fabricating photo detector

A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.

Display panel

A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer with a first state, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer with a second state, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region of the substrate. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.

Photo detector and method for fabricating the same

The ROM device comprises a number of memory cells each is constructed based on a MOS transistor, the memory cells in the ROM are arranged into a number of rows and a columns. A number of word lines each connects to the gates of each of the MOS transistors of all the memory cells in each of the rows. A number of bit lines each connects to one of the source/drain pair of each of the MOS transistors of all the memory cells in each of the columns. A multiplexer comprises a number of transmitting transistors, each of the transmitting transistors is connected to a corresponding one of the bit lines, forming a current flow path including the transmitting transistor, the connected bit line, and the memory cells correspondingly connected to the bit line. A sense amplifier is coupled to the multiplexer for sensing the current flowing therethrough the current flow path to output a corresponding sense output signal. The method for bypassing null-code sections to comprise programing the transmitting transistor in the current flow path into an off status when all memory cells in the column connecting to the bit line of the transmitting transistor is required to contain null code.

Method for bypassing null-code sections for read-only memory by access

A clamp circuit for a read-only-memory (ROM) device provides clamp voltages which can uniformly compensate for the parasitic capacitance on ROM word lines and improve the performance of the ROM device. The clamp circuit includes an active load, a plurality of amplifiers and a transmission gate. The amplifiers have various trip voltages and are controlled by different decoding signals for providing various clamp voltages to different word lines in the ROM device. Each amplifier is composed of a NOR gate and a transistor. The amplifier trip voltages can be easily set to desired values when designing NOR gate layout patterns without additional complicated processes being introduced into the fabrication methodology of a semiconductor integrated circuit.

Clamp circuit for read-only-memory devices

A ROM array with coding after metallization comprises a plurality of first bit lines, a plurality of second bit lines, a plurality of third bit lines, a plurality of word lines, a plurality of first control lines, a plurality of second control lines and a plurality of selecting lines. Memory cells of the ROM array are formed by the intersection of the word lines and the first and second bit lines, wherein the word lines are polysilicon gates and the bit lines are drain/source diffusion regions. The third bit lines are metal lines above the first bit lines. The third bit lines are not wide enough to cover spacings between the first and second bit lines, thus exposing spaces for code implantation. The first and second control lines intersect the first and second bit lines to form a number of switches for controlling data reading paths to The memory cells. The positions and ON/OFF states of the switches are designed to provide at least two data reading paths to each memory cell. Thus, the sensing currents in the bit lines are increased and become more uniform.

Read-only-memory array with coding after metallization

A ROM IC includes an extra bit line. The extra bit line outputs a first binary logic signal when a word line in a no-use area is attempted to be read and a second binary logic signal when a word line in a use area is attempted to be read. The output of the extra bit line overrides the normal output of the ROM when a word line in a no-use area is attempted to be read, so that the output of a read operation in the no-use area is always a predetermined binary value. This predetermined binary output value occurs in spite of the fact that because of a defect the actual logic value of a storage location in the word line to be read in the no-use area is other than a desired value. When a word line in the use area is read, the output of the extra bit line does not override the actual binary value stored in the word line. Using the extra bit line and associated override circuitry, a ROM IC with a few defects in a no-use area may still be used in an application. It should be noted that the addition of the extra bit line in the ROM does not significantly increase the amount of chip 'real estate' occupied by the ROM.

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Hsin-Chu, Taiwan

Hsin-Li Chen