United Integrated Circuits Corp.

United Microelectronics Corp.

Hsin-Kun Chu

A method of fabricating a capacitor is described. A dielectric layer is formed on a substrate. A node contact opening is formed in the dielectric layer to expose a portion of the substrate. A conductive layer is formed on the dielectric layer to cover the node contact opening. A ring trench is formed in the conductive layer above the node contact opening. An oxide layer is formed to fill the ring trench. An etching stop layer is formed to cover the oxide layer, the conductive layer encircled by the oxide layer, and a portion of the oxide layer beside the oxide layer. The etching stop layer defines a capacitor area. The conductive layer exposed by the etching stop layer is removed until the dielectric layer is exposed. The oxide layer and the etching stop layer are removed to expose the remaining conductive layer. A capacitor dielectric layer and a top electrode are formed in sequence to cover the remaining conductive layer.

Method of fabricating capacitor with a ring trench

A method of fabricating a DRAM capacitor. After forming a node contact opening in a dielectric layer on the substrate, a conductive layer having an annulus hollow is formed. A recess is formed on the conductive layer and a spacer is formed on the sidewall of the spacer, after which the annulus hollow is filled with an oxide layer. A photoresist layer for defining the capacitor region is formed. The etching stop layer, the oxide layer, and the spacer are removed to form the bottom electrode. Then, the dielectric layer and the upper electrode are formed in sequence.

Method of fabricating DRAM capacitor

An apparatus and method for performing a chemical vapor deposition (CVD) procedure to deposit an insulating layer when fabricating semiconductor integrated circuit devices over a silicon wafer. The CVD apparatus includes a buffer chamber for temporarily holding the wafer, and a chemical vapor deposition reaction chamber arranged at the periphery of the buffer chamber and communicating with the buffer chamber via a first access door. The CVD apparatus additionally includes a heating chamber, also arranged at the periphery of the buffer chamber, and communicating with the buffer chamber via a second access door, for performing a heating treatment of the wafer before the insulating layer is deposited on the wafer in the CVD reaction chamber. A transport arm is provided for transporting the wafer into and out of the heating chamber and the chemical vapor deposition reaction chamber.

Growing community of inventors

Hsinchu Hsien, Taiwan

Hsin-Kun Chu